Analytical model for ultra-thin body junctionless symmetric double gate MOSFETs in subthreshold regime

Jazaeri, Farzan; Barbut, Lucian; Koukab, Adil; Sallèse, Jean-Michel

doi:10.1016/j.sse.2013.02.001

Cited by 137 publications

(60 citation statements)

References 27 publications

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“…If N sd tends to infinity, then (19) tends to an expression close to the ones obtained in [10,22] based on the often quoted Liu model [21], except that the expression of k now reflects the position of the leakiest path. The omission of this correction leads to large inaccuracies, as shown in Fig.…”

Section: Derivation Of the Ss Expressionsupporting

confidence: 55%

Compact modeling of subthreshold swing in double gate and nanowire MOSFETs, for Si and GaAs channel materials

Hiblot

Rafhay

Bœuf

et al. 2015

Solid-State Electronics

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Section: Derivation Of the Ss Expressionsupporting

confidence: 55%

Compact modeling of subthreshold swing in double gate and nanowire MOSFETs, for Si and GaAs channel materials

Hiblot

Rafhay

Bœuf

et al. 2015

Solid-State Electronics

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“…The Poisson's equation along the direction perpendicular to the Si substrate for the mobile charge (electrons) can be expressed as [29] …”

Section: Device Structure and Potential Modelmentioning

confidence: 99%

“…The second order potential approximation can be represented by a simple parabolic function as in [29] ϕðx; yÞ ¼ ϕ S ðxÞþK 1 ðxÞy þ K 2 ðxÞy 2 ð7Þ…”

Section: Device Structure and Potential Modelmentioning

confidence: 99%

Analytical surface potential modeling and simulation of junction-less double gate (JLDG) MOSFET for ultra low-power analog/RF circuits

Roy

Gupta

Rai

2015

Microelectronics Journal

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“…A number of JLFET structures have been proposed with variations in topologies, such as single gate bulk planar JLFET [3], single gate silicon-on-insulator (SOI) JLFET [4], multi-gate nanowire junctionless transistors [5], gate-all-around nanowire junctionless transistors [6], as well as junctionless tunnel FET [7]. However, little attention is given on the gate materials in JLFET as well as the processing sequence on the gate.…”

Section: Introductionmentioning

confidence: 99%

Influence of Gate Material and Process on Junctionless FET Subthreshold Performance

Riyadi¹,

Sukawati²,

Prakoso³

et al. 2016

IJECE

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The recent progress of dimension scaling of electronic device into nano scale has motivated the invention of alternative materials and structures. One new device that shows great potential to prolong the scaling is junctionless FET (JLFET). In contrast to conventional MOSFETs, JLFET does not require steep junction for source and drain. The device processing directly influence the performance, therefore it is crucial to understand the role of gate processing in JLFET. This paper investigates the influence of gate material and process on subthreshold performance of junctionless FET, by comparing four sets of gate properties and process techniques. The result shows that in terms of subthreshold slope, JLFET approaches near ideal value of 60 mV/decade, which is superior than the SOI FET for similar doping rate. On the other hand, the threshold value shows different tendencies between those types of device.

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Analytical model for ultra-thin body junctionless symmetric double gate MOSFETs in subthreshold regime

Cited by 137 publications

References 27 publications

Compact modeling of subthreshold swing in double gate and nanowire MOSFETs, for Si and GaAs channel materials

Compact modeling of subthreshold swing in double gate and nanowire MOSFETs, for Si and GaAs channel materials

Analytical surface potential modeling and simulation of junction-less double gate (JLDG) MOSFET for ultra low-power analog/RF circuits

Influence of Gate Material and Process on Junctionless FET Subthreshold Performance

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