Analytical model of threshold voltage degradation due to localized charges in gate material engineered Schottky barrier cylindrical GAA MOSFETs

Abstract

The threshold voltage degradation due to the hot carrier induced localized charges (LC) is a major reliability concern for nanoscale Schottky barrier (SB) cylindrical gate all around (GAA) metal-oxide-semiconductor field-effect transistors (MOSFETs). The degradation physics of gate material engineered (GME)-SB-GAA MOSFETs due to LC is still unexplored. An explicit threshold voltage degradation model for GME-SB-GAA-MOSFETs with the incorporation of localized charges (N it ) is developed. To accurately model the threshold voltage the minimum channel carrier density has been taken into account. The model renders how +/− LC affects the device subthreshold performance. One-dimensional (1D) Poisson's and 2D Laplace equations have been solved for two different regions (fresh and damaged) with two different gate metal work-functions. LCs are considered at the drain side with low gate metal work-function as N it is more vulnerable towards the drain. For the reduction of carrier mobility degradation, a lightly doped channel has been considered. The proposed model also includes the effect of barrier height lowering at the metal-semiconductor interface. The developed model results have been verified using numerical simulation data obtained by the ATLAS-3D device simulator and excellent agreement is observed between analytical and simulation results.

Ambipolarity reduction in DMG asymmetric vacuum dielectric Schottky Barrier GAA MOSFET to improve hot carrier reliability

“…The carrier transport efficiency increases and the lifetime of the device enhance [11], [20], [21]. To reduce the ambipolar behaviour (I off ) in SB-CGAA MOSFET an Asymmetric Vacuum Gate Dielectric Schottky Barrier MOSFET structure has been proposed [19].…”

“…Using the boundary conditions (9a-9c) form reference [11] and (8a-8b) the solution of 1D Poisson's equation (6) in three different regions is obtained as:…”

“…At nanoscale the junction depletion width (p-n) at SourceChannel (S-C) and Channel-Drain (C-D) junctions can not be neglected as it degrades the ON current due to increased S-C and C-D resistance [5][6][7][8] and is actively involved in MOSFET device performance. The Schottky Barrier (SB) Cylindrical Gate All Around (CGAA) MOSFET with lightly doped channel have attracted attention [9][10][11][12] to overcome the device fabrication challenges like abrupt source/drain formation as it offers low resistivity (ρ c ~10 -9 Ω.cm) of metallic source drain and no depletion in S/D regions [13]. It also reduces thermal budget of fabrication process [14].…”

“…The lightly doped AV-SB-CGAA MOSFET ensures the lesser carrier mobility degradation. Dual Metal Gate has been employed to reduce the hot carrier assisted trap charge generation [11], [20]- [21]. In the present work analytical model for recently proposed DMG-AV-SB CGAA device has been developed incorporating the effect of Localized Charges [LC].…”

“…To avoid the carrier mobility degradation due to the coulomb scattering at high channel doping, a lightly doped (N A = 10 15 cm -3 ) channel region with uniform doping has been considered and is shown in figure 1 (a). The device channel length (L) is restricted up to 40 nm and radius 5 nm so the quantum mechanical effects are neglected for this length [11]. In this analysis the thickness of gate dielectric = 2 nm, SiO 2 permittivity ε SiO2 = 3.9, vacuum dielectric permittivity ε Vacu = 1, Gate 1 metal workfunction Φ M1 = 4.8 eV (WSi 2 ), Gate 2 metal workfunction Φ M2 = 4.4 eV (Ti), and Source/Drain metal workfunction Φ S/D = 4.1 eV (Al) have been considered.…”