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In this work, a hetero structure gate-drain underlap (UL) Schottky barrier (SB) Field Effect Transistor (FET) is explored to achieve high device performance compared with high-k and low-k hetero structure SB FET (HSBFET). The effects of gate drain UL junction on the performances of UL-HSBFETs have been studied in terms of electrical characteristics including on-current (I on), subthreshold swing, I on /I off ratio, ambipolar conduction, and I off current. The low on-state current of silicon-based SB FETs can be enhanced by introducing the low bandgap silicon germanium material. Gate-drain UL and silicon germanium channel with low barrier height provides less tunnelling width which enhances the carrier injection at on-state compared with low-k and high-k HSBFET. Further, the proposed UL-HSBFET suppresses the ambipolar conduction due to holes. In contrast to conventional high-k and low-k HSBFET that suffers from severe ambipolar conduction, the UL-HSBFET device reduces the conduction at drain-channel junction with increasing the UL length to 5, 10, 15, and 20 nm. This provides better radio frequency performances with improved carrier capability of the proposed device. Therefore, UL-HSBFET device can be one of the best possible competitor for high-frequency application. The performance comparison of all the devices is carried out using Technology Computer-Aided Design (TCAD) simulator.

This paper presents the analytical model of threshold voltage for hetero‐dielectric dual material gate Schottky barrier (SB) metal oxide semiconductor field effect transistor (MOSFET). The threshold voltage model is derived on the basis of the surface potential model. The threshold voltage is extracted using transconductance change method. The two‐dimensional surface potential, electric field, and threshold voltage model for the hetero‐dielectric dual material gate SB‐MOSFET are developed using 2‐D Poisson's equation, which satisfies the boundary conditions. Moreover, the model precisely depict the impact of hetero‐gate dielectric and gate oxide thickness on the surface potential, and threshold voltage of the hetero‐dielectric dual material gate SB and compared with single material gate SB‐MOSFET. Finally, a good agreement between the model results and numerical simulated results is achieved.

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