Analytical Modeling of Double Gate Graded-Channel SOI Transistors for Analog Applications

Abstract

In this work we present the development of an analytical model for double gate (DG) Silicon-on-Insulator (SOI) nMOSFET transistor with graded-channel (GC), valid from weak inversion to strong inversion. Atlas numerical two-dimensional simulations and experimental results are used to validate the proposed model. Good agreement between simulated, modeled and experimental results is demonstrated.