Analytical Single-Electron Transistor (SET) Model for Design  and Analysis of Realistic SET Circuits

Uchida, Ken; Matsuzawa, K.; Koga, J.; Ohba, R.; Takagi, Shin; Toriumi, Akira

doi:10.1143/jjap.39.2321

Cited by 106 publications

(54 citation statements)

References 9 publications

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“…However, they are too slow for analysis of large circuits. Uchida et al proposed an analytical SET model and incorporated it into SPICE [23]. Recently, Inokawa et al extended this model to a more general form to include asymmetric SETs [24].…”

Section: A Past Workmentioning

confidence: 99%

See 1 more Smart Citation

Characterization of Single-Electron Tunneling Transistors for Designing Low-Power Embedded Systems

Zhu

Dick

et al. 2009

IEEE Trans. VLSI Syst.

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Abstract-Minimizing power consumption is vitally important in embedded system design; power consumption determines battery lifespan. Ultra-low-power designs may even permit embedded systems to operate without batteries by scavenging energy from the environment. Moreover, managing power dissipation is now a key factor in integrated circuit packaging and cooling. As a result, embedded system price, size, weight, and reliability are all strongly dependent on power dissipation.Recent developments in nanoscale devices open new alternatives for low-power embedded system design. Among these, single-electron tunneling transistors (SETs) hold the promise of achieving the lowest power consumption. Unfortunately, most analysis of SETs has focused on single devices instead of architectures, making it difficult to determine whether they are appropriate for low-power embedded systems.Evaluating the use of SETs in large-scale digital systems requires novel architectural and circuit design. SET-based design imposes numerous challenges resulting from low driving strength, relatively large static power consumption, and the presence of reliability problems resulting from random background charge effects. We propose a fault-tolerant, hybrid SET/CMOS, reconfigurable architecture, named IceFlex, that can be tailored to specific requirements and allows trade-offs among power consumption, performance requirements, operation temperature, fabrication cost, and reliability. Using IceFlex as a testbed, we characterize the benefits and limitations of SETs in embedded system designs. In particular, we focus on the use of SETs in room-temperature ultra-low-power embedded systems such as wireless sensor network nodes. We also consider higherperformance applications such as multimedia consumer electronics. We see this work as a first step in determining the potential of ultra-low-power embedded system design using SETs.

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Section: A Past Workmentioning

confidence: 99%

“…Researchers have reported device operation at each level but the 40k B T requirement is more reliable. At charging energies over 10k B T , the model we use is accurate to within 4% of the time-dependent master equation [23,38].…”

Section: ) Junction Resistancementioning

confidence: 99%

Characterization of Single-Electron Tunneling Transistors for Designing Low-Power Embedded Systems

Zhu

Dick

et al. 2009

IEEE Trans. VLSI Syst.

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“…We explicitly consider the effects of thermal noise; they are reflected in our design decisions and their impacts on power consumption and performance are considered. At charging energies over ½¼ Ì , the model we use is accurate to within 4% of the time-dependent master equation [14,18].…”

Section: Iiia5) Reliability Implicationsmentioning

confidence: 99%

“…SIMON [12] and MOSES [13] are the two most popular SET simulators which, nevertheless, are not suitable for circuit analysis due to large runtimes when characterizing systems containing more than a few SETs. Uchida et al proposed an analytical SET model and incorporated it into SPICE [14]. Recently, Inokawa et al extended this model to a more general form to include asymmetric SETs [15].…”

Section: Introductionmentioning

confidence: 99%

Towards an ultra-low-power architecture using single-electron tunneling transistors

Zhu¹,

Shang³

et al. 2007

Proceedings of the 44th Annual Conference on Design Automation - DAC '07

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Minimizing power consumption is vitally important in embedded system design; power consumption determines battery lifespan. Ultralow-power designs may even permit embedded systems to operate without batteries, e.g., by scavenging energy from the environment. Moreover, managing power dissipation is now a key factor in integrated circuit packaging and cooling. As a result, embedded system price, size, weight, and reliability are all strongly dependent on power dissipation.Recent developments in nanoscale devices open new alternatives for low-power embedded system design. Among these, single-electron tunneling transistors (SETs) hold the promise of achieving the lowest power consumption. However, SETs impose unique design constraints that strongly influence architectural and circuit-level decisions. Unfortunately, most analysis of SETs has focused on single devices instead of architectures, making it difficult to determine whether they are appropriate for low-power embedded systems.This article presents possible uses of SETs in high-performance and battery-powered embedded system design. The resulting fault-tolerant, hybrid SET/CMOS, reconfigurable architecture can be tailored to specific requirements and allows trade-offs among power consumption, performance, operation temperature, fabrication cost, and reliability. This work is a first step in evaluating the system-level potential of reducing power consumption by using SETs.

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“…Until now, only two compact analytical models (Uchida et al, for single gate resistive symmetric SET [1] and Mahapatra et al, for asymmetric SET [2]) have been reported. We propose an improved model, which is more flexible and can be adapted for symmetrical and asymmetrical device geometries.…”

Section: Introductionmentioning

confidence: 99%

Modelling transport in single electron transistor

Hiền

Thao

Minh

2009

J. Phys.: Conf. Ser.

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Abstract. We introduce a model of single electron transistor (SET). Simulation programme of SET is used as the exploratory tool in order to gain better understanding of process and device physics. This simulator includes a graphic user interface (GUI) in Matlab. The SET was simulated using GUI in Matlab to get current-voltage (I-V) characteristics. In addition, effects of device capacitance, bias, temperature on the I-V characteristics were obtained. In this work, we review the capabilities of the simulator of the SET. Typical simulations of the obtained I-V characteristics of the SET are presented.

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Analytical Single-Electron Transistor (SET) Model for Design and Analysis of Realistic SET Circuits

Cited by 106 publications

References 9 publications

Characterization of Single-Electron Tunneling Transistors for Designing Low-Power Embedded Systems

Characterization of Single-Electron Tunneling Transistors for Designing Low-Power Embedded Systems

Towards an ultra-low-power architecture using single-electron tunneling transistors

Modelling transport in single electron transistor

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