Towards an ultra-low-power architecture using single-electron tunneling transistors

Abstract

Minimizing power consumption is vitally important in embedded system design; power consumption determines battery lifespan. Ultralow-power designs may even permit embedded systems to operate without batteries, e.g., by scavenging energy from the environment. Moreover, managing power dissipation is now a key factor in integrated circuit packaging and cooling. As a result, embedded system price, size, weight, and reliability are all strongly dependent on power dissipation.Recent developments in nanoscale devices open new alternatives for low-power embedded system design. Among these, single-electron tunneling transistors (SETs) hold the promise of achieving the lowest power consumption. However, SETs impose unique design constraints that strongly influence architectural and circuit-level decisions. Unfortunately, most analysis of SETs has focused on single devices instead of architectures, making it difficult to determine whether they are appropriate for low-power embedded systems.This article presents possible uses of SETs in high-performance and battery-powered embedded system design. The resulting fault-tolerant, hybrid SET/CMOS, reconfigurable architecture can be tailored to specific requirements and allows trade-offs among power consumption, performance, operation temperature, fabrication cost, and reliability. This work is a first step in evaluating the system-level potential of reducing power consumption by using SETs.

Reconfigurable Boolean Logic Using Magnetic Single-Electron Transistors

“…1(a). The key element of this structure is the magnetic gate electrode, an epitaxially grown Ga 0.94 Mn 0.06 As layer on GaAs that acts as a back-gate with easy-axis directions [110] and [1][2][3][4][5][6][7][8][9][10]. A magnetic field B=0.7 T, larger that the saturation field B s ≈0.3 T, is applied to rotate the magnetization M with respect to the [001] direction (φ=0 • ).…”

“…A magnetic field B=0.7 T, larger that the saturation field B s ≈0.3 T, is applied to rotate the magnetization M with respect to the [001] direction (φ=0 • ). The angle θ with respect to the [1][2][3][4][5][6][7][8][9][10] direction is kept equal to 90 • in all measurements. The results presented here are independent of the magnitude of B for B > B s .…”

“…Reconfiguration of the logic functions at each individual device promises even more compact and flexible circuit design [1][2][3][4][5] . However, the implementation of such reconfigurable logic using single-electron transistors (SETs) 6,7 is appealing because SETs have good scalability, one of the lowest energy-per-switching-event 8 and the possibility to combine their electrical properties with magnetic elements [9][10][11][12][13][14] . There have been several proposals to implement programmable SET logic by using the charge degree of freedom such as fixed gate voltages 15 , non-volatile charge nodes 16,17 and the spin degree of freedom [18][19][20] .…”

Design space exploration and data memory architecture design for a hybrid nano/CMOS dynamically reconfigurable architecture

“…Strukov and Likharev [2005] and Tu et al [2007] proposed CMOL, a hybrid cellbased FPGA-like architecture, combining a CMOS stack, two levels of parallel nanowires, and molecular-scale nanodevices formed between the nanowires at every crosspoint to provide both logic operation and interconnection. Zhu et al [2007] proposed an ultra-low-power reconfigurable architecture using a hybrid design based on single-electron tunneling transistors and CMOS. These designs achieve improvements in integration density, performance, or power consumption.…”