Analytical Threshold Model for Nanoscale Cylindrical Surrounding-Gate Metal–Oxide–Semiconductor Field Effect Transistor with High-κ Gate Dielectric and Tri-Material Gate Stack

Abstract

A novel cylindrical surrounding-gate metal-oxide-semiconductor field effect transistor with highgate dielectric and tri-material gate stack (TMGCSG MOSFET) is presented. The performance of the new structure is studied by developing physics-based analytical models for surface potential, electric field, and threshold voltage. It is found that TMGCSG MOSFET can effectively suppress short-channel effects and hot-carrier effects, and simultaneously improve carrier transport efficiency. It is also revealed that threshold voltage roll-off for TMGCSG MOSFET can be significantly reduced by adopting both a small effective stack-gate oxide thickness and a small radius silicon channel. The accuracy of the analytical models is verified by its good agreement with the three-dimensional numerical device simulator DESSIS.

Drain Current Model of a Four-Gate Dielectric Modulated MOSFET for Application as a Biosensor

“…The linear and saturation region drain current for the four-gate MOSFET is determined using the threshold voltage expression and three transistor modeling approach [29]- [31]. For the linear regime, the current in each region is calculated separately.…”

An analytic drain current model for long‐channel undoped gate stack surrounding‐gate MOSFETs including interface fixed charges

“…As planar single‐gate complementary metal–oxide–semiconductor (CMOS) scaling is approaching the limit imposed by the gate oxide tunneling and the serious short channel effects , innovative device structures such as double‐gate, triple‐gate, quadruple‐gate, and surrounding‐gate (SRG) metal–oxide–semiconductor field‐effect transistors (MOSFETs) are developed in order to continue scaling . By surrounding the channel with the gate completely, excellent gate control of SRG MOSFETs is achieved to suppress the short channel effects , and SRG MOSFETs can also be scaled to the shortest channel length possible for a given gate oxide thickness .…”