Analytical Threshold Voltage Model of Junctionless Double-Gate MOSFETs With Localized Charges

Abstract

An analytical threshold voltage model for a junctionless double-gate MOSFET with localized charges is developed. The model is derived based on 2-D Poisson's equation with parabolic potential approximation. The proposed model is verified by device simulation results. Threshold voltage dependencies on various device parameters are also analyzed. The proposed model can be used to estimate the threshold voltage degradation as caused by hot carrier effects and to provide a guideline for the optimization of junctionless transistors.

Ambipolarity reduction in DMG asymmetric vacuum dielectric Schottky Barrier GAA MOSFET to improve hot carrier reliability

“…The localize charges generated due to hot carriers are mainly prominent towards drain side [36]- [41]. The flat band voltage given in equation (9d)-(9f) changes, in three different regions due to the different gate metal workfunction and the existence of localized charges in region 2.…”

A Generalized Threshold Voltage Model of Tied and Untied Double-Gate Junctionless FETs for a Symmetric and Asymmetric Structure

“…Equation (9) becomes a typical quadratic equation when expanded, and the obtained solution is shown as (10), as shown at the bottom of this page. Because the back-gate is independently separated from the front-gate, V T is a function of the back-gate voltage.…”

“…To understand this different conduction mechanism analytically, several models have been introduced for double-gate junctionless transistors (DGJL-FETs). Current-voltage models have been introduced [6], [7] and analytical threshold voltage models have been developed [8]- [10] for symmetric DGJL-FETs. However, a general potential model represented with analytic formulas for tied and untied DGJL-FETs with corresponding symmetric and asymmetric structures has not yet been developed.…”

Threshold voltage modeling and performance comparison of a novel linearly graded binary metal alloy gate junctionless double gate metal oxide semiconductor field effect transistor

“…By virtue of their junctionless architecture, the JL devices eliminate the problems of impurity diffusion and sharp doping profile formation. As a result of this, the junctionless metal oxide semiconductor field effect transistors (JL MOSFET) exhibit superior turn-on and output characteristics [10][11][12][13], near ideal sub-threshold swing, sufficiently high ON current, and interesting temperature characteristics mainly due to the average temperature sensitivity of carrier mobility at an increased impurity concentration.…”