Analytical Transfer Functions Relating Power and Ground Voltage Fluctuations to Jitter at a Single-Ended Full-Swing Buffer

Hwang, Chulsoon; Kim, Jingook; Achkir, Brice; Fan, Jun

doi:10.1109/tcpmt.2012.2226723

Cited by 42 publications

(14 citation statements)

References 13 publications

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“…The MPCB process here is reliable, cost-effective, and easy to manufacture. Port 1 contains the signal terminal, which is connected to the high-Z o patch of UC (1,5) in L3 and the ground terminal, which is connected to the corresponding ground layers in L2 and L4. Port 2 consists of the signal terminal, which is connected to the high-Z o patch of UC (4,1) in L11.…”

Section: Resultsmentioning

confidence: 99%

“…The other type is an inter-VCA branch, which connects low-Z o patches in different tiers and different VCAs. In Figure 2a, for instance, the inter-VCA branch is highlighted to connect a low-Z o patch in UC (3,5) to a low-Z o patch in UC (4,4) . To more clearly explain the intra-/inter-VCA branches, only the low-Z o patches and VCA branches are shown in the other view point in Figure 2b, where the red and blue arrows point at the inter-VCA branches and intra-VCA branches, respectively.…”

Section: Geometrical Designmentioning

confidence: 99%

“…For the inter-VCA branch, the low-Z o patches in VCA 1 and VCA 4 contain one inter-VCA branch, whereas each low-Z o patch in VCA 2 and VCA 3 contains two inter-VCA branches. For example, UC (1,5) has an intra-VCA branch to connect with UC (1,5) and an inter-VCA branch to connect with UC (2,4) . For UC (3,5) , two inter-VCA branches are used to connect with UC (2,4) and UC (4,4) , whereas one intra-VCA branch connects it to UC (3,4) .…”

Section: Geometrical Designmentioning

confidence: 99%

“…Then, the noise source and victim can be vertically connected to UC (5,1) and UC (1,4) , respectively, through the via structures. The lateral distance between the noise source and a victim is extremely short because UC (5,1) and UC (1,4) are closely placed in the horizontal view. However, the noise source and a victim are sufficiently separated in the view of the Z o -lattice diagram, as shown in Figure 3.…”

Section: Characteristic-impedance Analysismentioning

confidence: 99%

“…Various devices such as RF, analog, memory, and digital chips are mounted on the MPCBs. Digital devices are known to generate wideband electromagnetic noise in the gigahertz (GHz) frequency range, which severely degrades the performance of the other circuits including themselves [1][2][3][4][5]. In addition, the noise source and victim devices are placed closely for the compact design.…”

Section: Introductionmentioning

confidence: 99%

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A Compact and Multi-Stack Electromagnetic Bandgap Structure for Gigahertz Noise Suppression in Multilayer Printed Circuit Boards

Kim

Ahn

2017

Applied Sciences

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Abstract:In modern printed electronics, the performances of a circuit and a device are severely deteriorated by the electromagnetic noise in the gigahertz (GHz) frequency range, such as the simultaneous switching noise and ground bounce noise. A compact and multi-stack electromagnetic bandgap (CMS-EBG) structure is proposed to suppress the electromagnetic noise over the GHz frequency range with a short distance between a noise source and a victim on multilayer printed circuit boards (MPCBs). The original configuration of the stepped impedance resonators is presented to efficiently form multiple stacks of EBG cells. The noise suppression characteristics of the CMS-EBG structure are rigorously examined using Floquet-Bloch analysis. In the analysis, dispersion diagrams are extracted from an equivalent circuit model and a full-wave simulation model. It is experimentally verified that the CMS-EBG structure suppresses the resonant modes over the wideband frequency range with a short source-to-victim distance; thus, this structure substantially mitigates GHz electromagnetic noise in compact MPCBs.

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Section: Resultsmentioning

confidence: 99%

Section: Geometrical Designmentioning

confidence: 99%

Section: Geometrical Designmentioning

confidence: 99%

Section: Characteristic-impedance Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Compact and Multi-Stack Electromagnetic Bandgap Structure for Gigahertz Noise Suppression in Multilayer Printed Circuit Boards

Kim

Ahn

2017

Applied Sciences

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A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers

et al. 2019

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This paper presents an efficient and generic method for analysis of power supply induced jitter (PSIJ) in a chain of CMOS inverters as well as tapered buffers due to multiple deterministic noise sources. Generalised semi-analytical relations between noise and PSIJ are developed using Thomas algorithm. The proposed analysis can be used for both cases of same size of inverters as well as tapered buffers, and also for considering the effect of on-chip and off-chip interconnects. The validity and the efficiency of the proposed modeling is demonstrated for various applications of chain of inverters such as buffers in clock distribution, delay locked loops and I/Os, etc. INDEX TERMS CMOS inverter, chain of inverters, clock-network, delay-line, I/O, jitter, power supply noise, power supply induced jitter, time interval error, tapered buffer. APPENDIX C FORMULATION OF TRI-DIAGONAL MATRIX FOR EXAMPLE-3

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Novel Observations and Physical Insights on PSIJ Behavior in CMOS Chain-of-Inverters

Illikkal

Tripathi

Sharma³

et al. 2022

IEEE Access

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Analytical Transfer Functions Relating Power and Ground Voltage Fluctuations to Jitter at a Single-Ended Full-Swing Buffer

Cited by 42 publications

References 13 publications

A Compact and Multi-Stack Electromagnetic Bandgap Structure for Gigahertz Noise Suppression in Multilayer Printed Circuit Boards

A Compact and Multi-Stack Electromagnetic Bandgap Structure for Gigahertz Noise Suppression in Multilayer Printed Circuit Boards

A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers

Novel Observations and Physical Insights on PSIJ Behavior in CMOS Chain-of-Inverters

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