Analyzing CUDA workloads using a detailed GPU simulator

Bakhoda, Ali; Yuan, George L.; Fung, Wilson Wai Lun; Wong, Henry; Aamodt, Tor M.

doi:10.1109/ispass.2009.4919648

Cited by 1,334 publications

(855 citation statements)

References 23 publications

Supporting

Mentioning

825

Contrasting

Unclassified

Order By: Relevance

“…GPU simulators running CUDA's intermediate language PTX such as GPUSim [4] or Ocelot [5] can offer a greater accuracy, but still run an unoptimized intermediate code instead of the instructions actually executed by a GPU.…”

Section: Barra a Functional Simulator Of Nvidia Gpusmentioning

confidence: 99%

Dynamic Detection of Uniform and Affine Vectors in GPGPU Computations

Collange

Defour

Zhang

2010

Lecture Notes in Computer Science

View full text Add to dashboard Cite

Abstract. We present a hardware mechanism which dynamically detects uniform and affine vectors used in Graphics Processing Units, to minimize pressure on the register file and reduce power consumption with minimal architectural modifications. A preliminary experimental analysis conducted with a simulator shows that this optimization can benefit up to 34 % of register file reads and 22 % of the computations of GPGPU applications.

show abstract

Section: Barra a Functional Simulator Of Nvidia Gpusmentioning

confidence: 99%

Dynamic Detection of Uniform and Affine Vectors in GPGPU Computations

Collange

Defour

Zhang

2010

Lecture Notes in Computer Science

View full text Add to dashboard Cite

show abstract

“…To model a GPU-based address space with an allocated set of MCs, we employ GPGPUsim [3] simulator, which already contains a module that implement multiple DDRbased MC-system. Memory transactions are generated by the multiple GPU caches and and treated in the memory module of GPGPUsim.…”

Section: Methodsmentioning

confidence: 99%

Insights on memory controller scaling in multi-core embedded systems

Marino¹,

2014

IJES

View full text Add to dashboard Cite

Abstract:In recent years, the growth on the number of cores as well as the frequency of cores along different processor generations has proportionally increased bandwidth needs simultaneously in both CPU and GPU systems. In order to address the communication latency between CPU and GPU memories in recent implementation of heterogeneous mobile embedded systems with hard or firm real-time requirements, sharing the same address space adds significant levels of contention. In addition, when heterogeneous cores are simultaneously present in a single system, memory parallelism is significantly restricted by a small amount of memory controllers (MCs). As a strategy to approach these significant levels of memory pressure, it is proposed in this paper evaluations of the impact of scaling MCs up to 4-8 units -limited by motherboard size for embedded purposes. Our findings show that performance is enhanced by a factor of 4x when employing only CPU cores, 4.6x when only GPU cores and finally, 2x when both CPU and GPU cores are simultaneously considered.

show abstract

“…For example, the GPU core configuration used in our evaluation employs a 24-stage pipeline with SIMD width of 8 (This is in line with a contemporary NVIDIA GTX280 architecture [11]. Similar pipeline configurations are also widely used in research GPU models [12,13].). Hence, assuming 4 extra stages for tolerating shared memory bank conflicts, the pipeline depth is increased from 24 stages to 28.…”

Section: Latency and Bandwidth Implicationsmentioning

confidence: 99%

“…Experimental Setup: We use a modified version of GPGPU-Sim [12], which is a cycle accurate full system simulator for GPUs implementing ptx ISA [19]. We model GPU cores with a 24-stage pipeline similar to contemporary implementations [11,13].…”

Section: Experimental Evaluationmentioning

confidence: 99%

Addressing GPU On-Chip Shared Memory Bank Conflicts Using Elastic Pipeline

Gou

Gaydadjiev

2012

Int J Parallel Prog

View full text Add to dashboard Cite

One of the major problems with the GPU on-chip shared memory is bank conflicts. We analyze that the throughput of the GPU processor core is often constrained neither by the shared memory bandwidth, nor by the shared memory latency (as long as it stays constant), but is rather due to the varied latencies caused by memory bank conflicts. This results in conflicts at the writeback stage of the in-order pipeline and causes pipeline stalls, thus degrading system throughput. Based on this observation, we investigate and propose a novel Elastic Pipeline design that minimizes the negative impact of on-chip memory bank conflicts on system throughput, by decoupling bank conflicts from pipeline stalls. Simulation results show that our proposed Elastic Pipeline together with the co-designed bank-conflict aware warp scheduling reduces the pipeline stalls by up to 64.0 % (with 42.3 % on average) and improves the overall performance by up to 20.7 % (on average 13.3 %) for representative benchmarks, at trivial hardware overhead.

show abstract

Analyzing CUDA workloads using a detailed GPU simulator

Abstract: Modern Graphic Processing Units (GPUs)

Cited by 1,334 publications

References 23 publications

Dynamic Detection of Uniform and Affine Vectors in GPGPU Computations

Dynamic Detection of Uniform and Affine Vectors in GPGPU Computations

Insights on memory controller scaling in multi-core embedded systems

Addressing GPU On-Chip Shared Memory Bank Conflicts Using Elastic Pipeline

Contact Info

Product

Resources

About