Analyzing lockstep dual-core ARM cortex-A9 soft error mitigation in freeRTOS applications

Oliveira, Ádria Barros de; Rodrigues, Gennaro S.; Kastensmidt, Fernanda Lima

doi:10.1145/3109984.3110008

Cited by 19 publications

(14 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Another variable to take into account is the effect of using an operating system, which can be considered as another source of errors because it is not protected [19] and supposes an additional cost that may be unaffordable. For instance, authors in [15] proved that RTOS (Real-Time Operating System) has an impact on performance and reliability, achieved by their DCLS technique, which is similar to the bare-metal results. Also, authors in [16] conclude that the usage of parallelization APIs (Application Programming Interfaces) increases the occurrence of unexpected terminations that are caught by the operating system.…”

Section: Introductionmentioning

confidence: 53%

“…For example, a multi-threading strategy can be found in [13], which makes use of threading libraries and take advantage of resources present in the majority of operating systems. Whereas [14,15] use reconfigurable hardware as FPGAs to achieve a lockstep solution. These software approaches introduce large size and performance overheads that have to be taken into consideration.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Multi-Threaded Mitigation of Radiation-Induced Soft Errors in Bare-Metal Embedded Systems

Serrano-Cases¹,

Restrepo-Calle

Cuenca-Asensi³

et al. 2019

J Electron Test

View full text Add to dashboard Cite

This article presents a software protection technique against radiation-induced faults which is based on a multi-threaded strategy. Data triplication and instructions flow duplication or triplication techniques are used to improve system reliability and thus, ensure a correct system operation. To achieve this objective, a relaxed lockstep model to synchronize the execution of both, redundant threads and variables under protection on different processing units is defined. The evaluation was performed by means of simulated fault injection campaigns in a multi-core ARM system. Results show that despite being considered techniques that imply an evident overhead in memory and instructions (Duplication With Comparison and Re-Execution -DWC-R and Triple Modular Redundancy -TMR), spreading the replicas in different instruction flows not only produce similar results than classic techniques, but also improves the computational and recovery time in presence of soft-errors. In addition, this paper highlights the importance of protecting memory-allocated data, since the instruction flow triplication is not enough to improve the overall system reliability.

show abstract

Section: Introductionmentioning

confidence: 53%

Section: Introductionmentioning

confidence: 99%

Multi-Threaded Mitigation of Radiation-Induced Soft Errors in Bare-Metal Embedded Systems

Serrano-Cases¹,

Restrepo-Calle

Cuenca-Asensi³

et al. 2019

J Electron Test

View full text Add to dashboard Cite

show abstract

“…Lockstep [17], [18] is a micro-synchronization variant of the processor replication techniques. Lockstep works by executing the same application simultaneously and symmetrically in two identical processors.…”

Section: Related Workmentioning

confidence: 99%

Online Error Detection Through Trace Infrastructure in ARM Microprocessors

Pena-Fernandez

Lindoso

Entrena

et al. 2019

IEEE Trans. Nucl. Sci.

View full text Add to dashboard Cite

This work presents a solution for error detection in ARM microprocessors based on the use of the trace infrastructure. This approach uses the Program and Instrumentation Trace Macrocells that are part of ARM's CoreSight™ architecture to detect control-flow and data-flow errors, respectively. The proposed approach has been tested with low-energy protons. Experimental results demonstrate high accuracy with up to 95% of observed errors detected in a commercial microprocessor with no hardware modification. In addition, it is shown how the proposed approach can be useful for further analysis and diagnosis of the cause of errors.

show abstract

“…As part of the efforts for developing solutions to address the demands of Autonomous Driving, industry and academia are investing in research on several related areas. Several works are exploring aspects of fault-tolerance in hardware architectures [1], [2], software design [3], operational systems [4], among others. [5] provides a broader look on specific reliability challenges for autonomous systems, for both automotive and robotics.…”

Section: Introductionmentioning

confidence: 99%

Special Session: AutoSoC - A Suite of Open-Source Automotive SoC Benchmarks

Silva

Bagbaba

Ruospo

et al. 2020

2020 IEEE 38th VLSI Test Symposium (VTS)

View full text Add to dashboard Cite

The current demands for autonomous driving generated momentum for an increase in research in the different technologies required for these applications. Nonetheless, the limited access to representative designs and industrial methodologies poses a challenge to the research community. Considering this scenario, there is a high demand for an open-source solution that could support development of research targeting automotive applications. This paper presents the current status of AutoSoC, an automotive SoC benchmark suite that includes hardware and software elements and is entirely open-source. The objective is to provide researchers with an industrial-grade automotive SoC that includes all essential components, is fully customizable, and enables analysis of functional safety solutions and automotive SoC configurations. This paper describes the available configurations of the benchmark including an initial assessment for ASIL B to D configurations.

show abstract

Analyzing lockstep dual-core ARM cortex-A9 soft error mitigation in freeRTOS applications

Cited by 19 publications

References 19 publications

Multi-Threaded Mitigation of Radiation-Induced Soft Errors in Bare-Metal Embedded Systems

Multi-Threaded Mitigation of Radiation-Induced Soft Errors in Bare-Metal Embedded Systems

Online Error Detection Through Trace Infrastructure in ARM Microprocessors

Special Session: AutoSoC - A Suite of Open-Source Automotive SoC Benchmarks

Contact Info

Product

Resources

About