Analyzing the Effectiveness of a Frame-Level Redundancy Scrubbing Technique for SRAM-based FPGAs

Tonfat, Jorge; Kastensmidt, Fernanda Lima; Rech, Paolo; Reis, Ricardo; Quinn, Heather

doi:10.1109/tns.2015.2489601

Cited by 28 publications

(19 citation statements)

References 15 publications

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“…However, since the reconfiguration frames for these sub-components are different, the average number of frames recovered for these sub-components differ. Table VI compares the average number of frames reconfigured per error, the average recovery time and the energy expended to repair the error assuming each frame write consumes 535 nJ [15]. The proposed fine-grained DPR approach to MER is listed as MER/FDPR and its performance is compared with, on the one hand, a more conventional approach to MER in which errors that occur outside the reconfigurable modules are recovered by scrubbing the device (MER/Scrub) [2], and on the other, by triggering a scrub whenever any error is detected in the system (Triggered Scrub).…”

Section: ) Fault Injection Resultsmentioning

confidence: 99%

Fine-grained module-based error recovery in FPGA-based TMR systems

Zhao

Agiakatsikas

Nguyen

et al. 2016

2016 International Conference on Field-Programmable Technology (FPT)

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Space processing applications deployed on SRAMbased Field Programmable Gate Arrays (FPGAs) are vulnerable to radiation-induced Single Event Upsets (SEUs). Compared with the well-known SEU mitigation solution-Triple Modular Redundancy (TMR) with configuration memory scrubbing-TMR with module-based error recovery (MER) is notably more energy efficient and responsive in repairing soft-errors in the system. Unfortunately, TMR-MER systems also need to resort to scrubbing when errors occur in sub-components, such as nets, which are not recovered by MER. This paper addresses this problem by proposing a fine-grained module-based error recovery technique that without additional system hardware can localize and correct errors that classic MER fails to do. We evaluate our proposal via a fault-injection campaign on a Xilinx Artix-7 application circuit and compare the reliability, the error correction latency and the energy cost of repairing errors, of our proposal with those of a conventional MER approach and with periodic and on-demand blind scrubbing. We find the reliability of our proposal to be the highest and the energy expenditure to be the lowest amongst those methods considered.

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Section: ) Fault Injection Resultsmentioning

confidence: 99%

Fine-grained module-based error recovery in FPGA-based TMR systems

Zhao

Agiakatsikas

Nguyen

et al. 2016

2016 International Conference on Field-Programmable Technology (FPT)

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“…It is possible to envisage different methods for generating the redundant copies. For instance, in [18], redundant frames are generated by replicating the same layout, and therefore the same configuration, in different identical subsets of the gate array. The redundant layouts are also used to provide redundant functionality and to majority vote the logic outputs in real-time.…”

Section: Majority-voting-based Configuration Scrubbingmentioning

confidence: 99%

Custom Scrubbing for Robust Configuration Hardening in Xilinx FPGAs

et al. 2019

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The usage of SRAM-based Field Programmable Gate Arrays on High Energy Physics detectors is mostly limited by the sensitivity of these devices to radiation-induced upsets in their configuration. These effects may alter the functionality until the next reconfiguration of the device. In this work, we present the radiation testing of a high-speed serial link hardened by a new, custom scrubber designed for Xilinx FPGAs. We compared the performance of our scrubber to the Xilinx Single Event Mitigation (SEM) controller and we measured the impact of the scrubbers on the reliability of the link. Our results show that our scrubber may improve reliability up to 23 times over the SEM.

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“…For each simulation, the size of each triplicated module, as measured in number of essential bits, was chosen randomly in a range from 10,000 to 2,000,000 bits using one of three size distributions: uniform, quadratic and exponential. For a given number of system components (3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16)(17)(18)(19)(20) and at each orbit level (LEO and GEO), we evaluated the performance of each schedule (VRVC, round robin, VSE) over five trials for each module size distribution (uniform, quadratic and exponential). Please note that there is no difference in hardware cost between VRVC and RR as both are controlled by a programmable RC.…”

Section: Assumptions and Implementationsmentioning

confidence: 99%

Scheduling configuration memory error checks to improve the reliability of FPGA‐based systems

Nguyen

Cetin²,

Diessel³

2018

IET Computers & Digital Techniques

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Field-programmable gate arrays are susceptible to radiation-induced single event upsets. These are commonly dealt with using triple modular redundancy (TMR) and module-based configuration memory error recovery (MER). By triplicating components and voting on their outputs, TMR helps localise configuration memory errors, and by reconfiguring faulty components, MER swiftly corrects them. However, the order in which TMR voters are checked inevitably impacts the overall system reliability. In this study, the authors outline an approach for computing the reliability of TMR-MER systems that consist of finitely many components. They demonstrate that system reliability is improved when the more vulnerable components are checked more frequently than when they are checked in round-robin order. They propose a genetic algorithm for finding a voter checking schedule that maximises the reliability of TMR-MER systems. Results indicate that the mean time to failure (MTTF) of these systems can be increased by up to 400% when variable-rate voter checking (VRVC) is used instead of round robin. They show that VRVC achieves 15-23% increase in MTTF with a 10× reduction in checking frequency to reduce system power. They also found that VRVC detects errors 44% faster on average than round robin. Nomenclature Symbol Definition N number of TMR components in the system Ck component k, k = 1, …, N O kn Ck is observed for the nth time by checking its voter(s) Δt o time period between successive voter observations (assumed to be constant for a given system setting) Δt dk time period between two consecutive observations of Ck Δt rk time period to recover a faulty module of Ck Δt k total time period over which Ck can fail Δt di j time period between successive observations of Ci and Cj Δt d′i j average time period between two consecutive observations of Ci in the interval between two consecutive observations of Cj IET Comput. Digit. Tech.

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Analyzing the Effectiveness of a Frame-Level Redundancy Scrubbing Technique for SRAM-based FPGAs

Cited by 28 publications

References 15 publications

Fine-grained module-based error recovery in FPGA-based TMR systems

Fine-grained module-based error recovery in FPGA-based TMR systems

Custom Scrubbing for Robust Configuration Hardening in Xilinx FPGAs

Scheduling configuration memory error checks to improve the reliability of FPGA‐based systems

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