2015 15th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing 2015
DOI: 10.1109/ccgrid.2015.164
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Analyzing the Impact of CPU Pinning and Partial CPU Loads on Performance and Energy Efficiency

Abstract: Abstract-While workload colocation is a necessity to increase energy efficiency of contemporary multicore hardware, it also increases the risk of performance anomalies due to workload interference. Pinning certain workloads to a subset of CPUs is a simple approach to increasing workload isolation, but its effect depends on workload type and system architecture. Apart from common sense guidelines, the effect of pinning has not been extensively studied so far. In this paper we study the impact of CPU pinning on … Show more

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Cited by 40 publications
(33 citation statements)
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“…Here we complement the results presented in our prior work [12] with a study of the overhead observed in the employed colocation solutions (KVM virtual machines and LXC containers) at partial loads.…”
Section: Introductionmentioning
confidence: 53%
See 1 more Smart Citation
“…Here we complement the results presented in our prior work [12] with a study of the overhead observed in the employed colocation solutions (KVM virtual machines and LXC containers) at partial loads.…”
Section: Introductionmentioning
confidence: 53%
“…The performance penalty is relatively strong for background loads around 0.5, yet almost negligible for both high and low background loads. 12 It appears to be weaker for LXC than for KVM, stronger for luindex and the Scala benchmarks and almost negligible for h2 and avrora. The latter correlates with the fact that ''per-thread'' is not always the foreground performance winner for avrora and h2, as shown in Fig.…”
Section: Background Load and Foreground Throughputmentioning
confidence: 95%
“…Prior work has demonstrated the importance of thread-to-core bindings in the overall performance of a parallelized application [8]. The task of discovering such optimal bindings is rather complex, given the structure of NUMA architectures [9].…”
Section: Related Work and Contributionsmentioning
confidence: 99%
“…Let also denote L * , the minimum makespan that can be achieved at the optimal assignments. Proposition 5.1 (Existence of Nash equilibria): Consider the load-balancing game characterized by the tuple I, A, {u i } i with a utility function defined by (8). Then, the set of pure Nash equilibria is non-empty, i.e., B NE = ∅.…”
Section: Convergence Analysismentioning
confidence: 99%
“…We use a linear performance function: on each machine, the influence a type t has on type t performance is a product of the load of type t and a coefficient α t ,t . The coefficient α t ,t describes how compatible t load is with t performance (the coefficient is similar to interference/affinity metrics proposed in [13,20]). Low values (0 ≤ α t ,t < 1) correspond with compatible types (e.g.…”
Section: Introductionmentioning
confidence: 99%