Analyzing the impact of heterogeneous blocks on FPGA placement quality

Abstract

In this paper we propose a quantitative approach to analyze the impact of heterogeneous blocks (H-blocks) on the FPGA placement quality. The basic idea is to construct synthetic heterogeneous placement benchmarks with known optimal wirelength to facilitate the quantitative analysis. To the best of our knowledge, this is the first work that enables the construction of wirelength-optimal heterogeneous placement examples. Besides analyzing the quality of existing placers, we further decompose the impacts of H-blocks from the architectural aspect and netlist aspect. Our analysis shows that a heterogeneous design hides the wirelength degradation by a more compact netlist than its homogeneous version; however, the heterogeneity results in a optimality gap of 52% in wirelength, where 25% is from architectural heterogeneity and 27% is from netlist heterogeneity. Therefore, new heterogeneous placement algorithms are needed to bridge the optimality gap and improve design quality.978-1-4799-6245-7/14/$31.00 ©2014 IEEE

Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration

“…The assumption is similar to the previous studies [Xilinx. 2011a;Beckhoff and et al 2013;Xu et al 2014]. Fig.…”