Analyzing the Sensitivity of GPU Pipeline Registers to Single Events Upsets

Condia, Josie E. Rodriguez; Goncalves, Marcio M.; Azambuja, Jose Rodrigo; Reorda, M. Sonza; Sterpone, Luca

doi:10.1109/isvlsi49217.2020.00076

Cited by 6 publications

(3 citation statements)

References 20 publications

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“…In contrast, the low-level micro-architectural evaluation can provide detailed information about the identification of vulnerable locations on most internal modules. In [20], [21], and [22], the authors proposed some reliability evaluation methodologies based on microarchitectural evaluation on RTlevel descriptions. In these works, fine-grain evaluation mainly uses two approaches to identify vulnerable locations: i) exhaustive evaluation of all sites in the modules, and ii) statistical samples of the sites in the modules.…”

Section: A Methodologies For Reliability Evaluationmentioning

confidence: 99%

An Effective Method to Identify Microarchitectural Vulnerabilities in GPUs

Condia

Rech

Santos

et al. 2022

IEEE Trans. Device Mater. Relib.

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Graphics Processing Units (GPUs) are increasingly adopted in several domains where reliability is fundamental, such as self-driving cars and autonomous systems. Unfortunately, GPU devices have been shown to have a high error rate, while the constraints imposed by real-time safety-critical applications make traditional (and costly) replication-based hardening solutions inadequate.This work proposes an effective methodology to identify the architectural vulnerable sites in GPUs modules, i.e. the locations that, if corrupted, most affect the correct instructions execution. We first identify, through an innovative method based on Register-Transfer Level (RTL) fault injection experiments, the architectural vulnerabilities of a GPU model. Then, we mitigate the fault impact via selective hardening applied to the flip-flops that have been identified as critical. We evaluate three hardening strategies: Triple Modular Redundancy (TMR), Triple Modular Redundancy against SETs (∆TMR), and Dual Interlocked Storage Cells (Dice flip-flops). The results gathered on a publicly available GPU Model (FlexGripPlus) considering functional units, pipeline registers, and warp scheduler controller show that our method can tolerate from 85% to 99% of faults in the pipeline registers, from 50% to 100% of faults in the functional units and up to 10% of faults in the warp scheduler, with a reduced hardware overhead (in the range of 58 % to 94% when compared with traditional TMR).Finally, we adapt the methodology to perform a complementary evaluation targeting permanent faults and identify critical sites prone to propagate fault effects across the GPU. We found that a considerable percentage (65% to 98%) of flip-flops that are critical for transient faults are also critical for permanent faults.

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Section: A Methodologies For Reliability Evaluationmentioning

confidence: 99%

An Effective Method to Identify Microarchitectural Vulnerabilities in GPUs

Condia

Rech

Santos

et al. 2022

IEEE Trans. Device Mater. Relib.

View full text Add to dashboard Cite

show abstract

“…-Detection with redundancy without diversity [163,6,191,178,199,57,73,138,99,164,34,170,120,140,77,127,139] and with diversity [13,14,8,12] -Detection and/or correction with coding (e.g., ECC) and checkers [57,120,169,139,108,124,125,140,132] -Recovery with re-execution or checkpoints [71,175,180,135,115,124] -Mitigation with shielding and reconfiguration [153,127,91,193] • Application-dependent:…”

Section: Random Hw Failuresmentioning

confidence: 99%

“…Processing Units Due to the limited public documentation, controllability and observability of SM architectures, few works target the reliability of SMs explicitly. In general, works attempt to improve SMs (and other components simultaneously) employing different software-based redundancy techniques for the whole SM, its cores only, or parts of those cores (e.g., pipeline registers [163]) using available underutilized resources in order to reduce the computing overhead [6,191,178,199,57,73]. Some authors combine software redundancy with diversity to mitigate common cause failures by, for instance, making redundant threads execute with some staggering in different cores [13,14,8].…”

Section: Componentsmentioning

confidence: 99%

GPU Devices for Safety-Critical Systems: A Survey

et al. 2022

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Graphics Processing Unit (GPU) devices and their associated software programming languages and frameworks can deliver the computing performance required to facilitate the development of next-generation high-performance safety-critical systems such as autonomous driving systems. However, the integration of complex, parallel and computationally demanding software functions with different safety-criticality levels on GPU devices with shared hardware resources contributes to several safety certification challenges. This survey categorizes and provides an overview of research contributions that address GPU devices’ random hardware failures, systematic failures and independence of execution.

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Investigating and Reducing the Architectural Impact of Transient Faults in Special Function Units for GPUs

Rodriguez Condia,

Guerrero-Balaguera,

Patiño Núñez

et al. 2024

J Electron Test

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Ensuring the reliability of GPUs and their internal components is paramount, especially in safety-critical domains like autonomous machines and self-driving cars. These cutting-edge applications heavily rely on GPUs to implement complex algorithms due to their implicit programming flexibility and parallelism, which is crucial for efficient operation. However, as integration technologies advance, there is a growing concern regarding the potential increase in fault sensitivity of the internal components of current GPU generations. In particular, Special Function Unit (SFU) cores inside GPUs are used in multimedia, High-Performance Computing, and neural network training. Despite their frequent usage and critical role in several domains, reliability evaluations on SFUs and the development of effective mitigation solutions have yet to be studied and remain unexplored. This work evaluates the impact of transient faults in the main hardware structures of SFUs in GPUs. In addition, we analyze the main overhead costs and benefits of developing selective-hardening mechanisms for SFUs. We focus on evaluating and analyzing two SFU architectures for GPUs (’fused’ and ’modular’) and their relations to energy, area, and reliability impact on parallel applications. The experiments resort to fine-grain fault injection campaigns on an RTL GPU model (FlexGripPlus) instrumented with both SFUs. The results on both SFU architectures indicate that fused SFUs (in commercial-grade devices) require lower area overhead (about 27%) for their integration in GPUs but are more vulnerable to transient faults (in up to 47% for the analyzed cases) and less power efficient (in up to 36.6%) than modular SFUs. Moreover, the reliability estimation shows that Modular SFUs are structurally more resilient than Fused ones in up to one order of magnitude. Similarly, selective-hardening mechanism based on Triple-Modular Redundancy (TMR) shows that coarse-grain strategies might increase the reliability of the overall SFUs under feasible overhead costs.

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Analyzing the Sensitivity of GPU Pipeline Registers to Single Events Upsets

Cited by 6 publications

References 20 publications

An Effective Method to Identify Microarchitectural Vulnerabilities in GPUs

An Effective Method to Identify Microarchitectural Vulnerabilities in GPUs

GPU Devices for Safety-Critical Systems: A Survey

Investigating and Reducing the Architectural Impact of Transient Faults in Special Function Units for GPUs

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