Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement

Tang, Hong; Manish, Sreenivasa; Rajski, J.; Keim, Martin; Benware, B.

doi:10.1109/ets.2007.11

Cited by 77 publications

(47 citation statements)

References 7 publications

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“…Therefore, the number of suspects increases more for single stuck-at faults. As shown in [3], a typical statistical learning algorithm can achieve very good results with diagnosis results with 90% accuracy. It is believed that the minimal impact on diagnosis accuracy and resolution for block level diagnosis on large industrial designs should have negligible impact on the final results of statistical yield learning.…”

Section: B Block Level Diagnosis On Industrial Designsmentioning

confidence: 91%

“…In this work, we focus on minimizing negative impact on diagnosis where design partitioning is used. As pointed out in [3] the minimal impact on diagnosis quality can be addressed by statistical learning algorithms and no impact should be seen for the final yield learning results.…”

Section: Introductionmentioning

confidence: 99%

“…However due to the continuously shrinking feature size and increasing complexity of designs, traditional yield learning methods such as inline inspection, memory bitmapping and test chips are becoming less effective. Statistical yield learning methods using volume diagnosis results have recently attracted great attention [1][2] [3][4] [5]. The diagnosis results for a large number of failing devices contain valuable defect information, such as types, locations, physical topology, design features, where various statistical methods can be applied to effectively identify systematic issues and uncover dominant defect mechanisms.…”

Section: Introductionmentioning

confidence: 99%

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On Using Design Partitioning to Reduce Diagnosis Memory Footprint

Xiao

Tang

Reddy

et al. 2011

2011 Asian Test Symposium

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Recently statistical yield learning based on volume diagnosis has become popular. Volume diagnosis requires a large amount of diagnosis results to be produced within a reasonable time. However, it is challenging to achieve the desired throughput for modern designs with continuously increasing size. In this paper, we propose a method to partition a design under diagnosis into blocks together with a diagnosis flow at the block level. The diagnosis throughput is improved because more diagnosis jobs can be run concurrently and each job runs faster due to the reduced memory. A measure is also proposed to estimate the impact on diagnosis caused by design partitioning. Experimental results on benchmark circuits and several industrial designs show that diagnosis using circuit blocks has minimal impact on diagnosis accuracy and resolution. It is also demonstrated that the proposed measure is a good metric in predicting the impact on diagnosis.

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Section: B Block Level Diagnosis On Industrial Designsmentioning

confidence: 91%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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On Using Design Partitioning to Reduce Diagnosis Memory Footprint

Xiao

Tang

Reddy

et al. 2011

2011 Asian Test Symposium

Self Cite

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show abstract

“…At 45nm technology and below, traditional yield learning techniques such as in-line inspection and memory bitmapping become less effective due to small features and large number of metal layers. Scan-based volume diagnosis methods have attracted great attentions recently [14,7,6] as alternative yield learning techniques. Volume diagnosis uses manufacturing test data to locate defects.…”

Section: Introductionmentioning

confidence: 99%

“…Most scan diagnosis techniques [14,5,12] that support compressed output responses consist of three steps. The first step is to find scan cells that capture errors.…”

Section: Introductionmentioning

confidence: 99%

Machine learning-based volume diagnosis

Wang

Wei

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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A survey of digital circuit testing in the light of machine learning

Pradhan

Bhattacharya

2020

WIREs Data Min & Knowl

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The insistent trend in today's nanoscale technology, to keep abreast of the Moore's law, has been continually opening up newer challenges to circuit designers. With rapid downscaling of integration, the intricacies involved in the manufacturing process have escalated significantly. Concomitantly, the nature of defects in silicon chips has become more complex and unpredictable, adding further difficulty in circuit testing and diagnosis. The volume of test data has surged and the parameters that govern testing of integrated circuits have increased not only in dimension but also in the complexity of their correlation. Evidently, the current scenario serves as a pertinent platform to explore new test solutions based on machine learning. In this survey, we look at various recent advances in this evolving domain in the context of digital logic testing and diagnosis. This article is categorized under: Algorithmic Development > Structure Discovery Technologies > Machine Learning Technologies > Prediction

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Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement

Cited by 77 publications

References 7 publications

On Using Design Partitioning to Reduce Diagnosis Memory Footprint

On Using Design Partitioning to Reduce Diagnosis Memory Footprint

Machine learning-based volume diagnosis

A survey of digital circuit testing in the light of machine learning

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