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A BIST (Built-In Self-Test) methodology that uses the circular BIST technique to perform a random test of sequential logic circuits is presented. The fault coverage obtained using this technique is supplemented by deterministic tests that are presented to the CUT (Circuit Under Test) by configuring the circular path as a partial scan chain. A CAD (Computer-Aided Design) tool for automating this methodology is described, a variety of heuristics for picking which flip-flops should be included in the circular path are evaluated and experimental results are presented.

3D IC testing is one of the major concern in the semiconductor industry today. Multiple subsequent testing of partial stack during 3D assembly is required due to the die stacking steps of thinning, alignment and bonding. In this paper we address the problem of minimizing the total time of partial stack and complete stack testing. We analyze how the stacking sequence of different System-on-Chips (SOCs) in a 3D Stacked Integrated Circuit (SIC) affects the total test time. We propose an algorithm to find this stacking sequence to achieve the minimum test time. Our algorithm is run on ITC'02 benchmarks and the results are shown.Index Terms-Three-dimensional integration, through silicon via, test access mechanism, system-on-a-chip (SOC)

The pervasiveness of graphs in today's real life systems is quite evident, where the system either explicitly exists as graph or can be readily modelled as one. Such graphical structure is thus a store house rich information. This has various implication depending on whether we are interested in a node or the graph as a whole. In this paper, we are primarily concerned with the later, that is, the inference that the structure of the graph influences the property of the real life system it represents. A model of such structural influence would be useful in inferencing useful properties of complex and large systems, like VLSI circuits, through its structural property. However, before we can apply some machine learning (ML) based technique to model such relationship, an effective representation of the graph is imperative. In this paper, we propose a graph representation which is lossless, linear-sized in terms of number of vertices and gives a 1-D representation of the graph. Our representation is based on Prufer encoding for trees. Moreover, our method is based on a novel technique, called GT -enhancement whereby we first transform the graph such that it can be represented by a singular tree. The encoding also provides scope to include additional graph property and improve the interpretability of the code.