Optimizing test time for core-based 3-d integrated circuits by a technique of bi-partitioning

Approach of genetic algorithm for power‐aware testing of 3D IC

“…However, the test time value 24,257 mentioned in [31] for TAM width 16 of SOC d695, is not at all possible to achieve as justified in [41]. Similarly, in comparison to [33], our proposed work for B ≤ 4 exhibits better performance in 6, 7, 2 and 7 cases for SOCs d695, p22810, p34392 48 20 NA 10 10 42,268 24,257 44,067 NA 42,268 42,268 24 NA 48 20 NA 18 18 28,389 21,953 28,546 NA 28,289 28,289 32 NA 48 20 NA 14 14 21,518 20,934 21,440 NA 21,440 21,440 40 NA 48 20 NA 26 74 17,677 18,604 17,684 NA 17, and p93791, respectively. In comparison to [34], our algorithm outperforms in almost all cases for SOCs p22810, p34392 and p93791 with respect to test time and in other few cases our performance is just equal.…”

“…Next, we have considered the maximum number of partition B ≤ 8 and executed our proposed algorithms for all the benchmarks. In comparison to [32][33][34], our proposed algorithm outperforms in almost all the cases for SOCs with respect to test time. In comparison to [31], our proposed algorithms exhibit better performance in 4, 5, 7 and 7 cases for SOCs d695, p22810, p34392 and p93791, respectively.…”

“…That is, among the different power values required by the different cores, we have to choose the maximum value of them and this is the limit up to which we can decrease P max . Addressing Problem II, a number of test access architectures and TAM optimisation methods have been proposed in literature [31][32][33][34][35].…”

“…We have compared the results of Algorithm 2 (Fig. 5) with literature [31][32][33][34]. Table 11 shows the experimental results for different TAM widths.…”

“…For each SOC, the TAM widths chosen have seven instances 16,24,32,40,48,56 and 64. Columns 3, 4, 5 and 6 depict TSV limits in a 3D partition as reported in [31][32][33][34], while our work considering the partitions, B ≤ 4 and B ≤ 8 for Columns 7 and 8 depict the TSV limit. Similarly, the columns 9, 10, 11 and 12 represent the test times in the number of clock cycles (#CC) as in [31][32][33][34], while our proposed work considering B ≤ 4 and B ≤ 8 is represented in columns 13 and 14, respectively.…”