Annealing Effects on Ge/SiO<sub>2</sub> Interface Structure in Wafer-Bonded Germanium-on-Insulator Substrates

Yoshitake, Osamu; Kikkawa, Jun; Nakamura, Yoshiaki; Toyoda, Eiji; Isogai, Hiromichi; Izunome, Koji; Sakai, Akira

doi:10.1143/jjap.50.04da13

Cited by 10 publications

(11 citation statements)

References 21 publications

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“…A smooth morphology was observed at the interface after annealing at 400qC, which was similar to the case after the 300qC preliminary annealing (6). On the other hand, nanometer-sized mound-like objects were frequently seen at the interfaces after annealing at 500700qC, as indicated by the arrows in Figs.…”

Section: Atomic and Chemical Structures Of Ge/box Interfaces In Goi Ssupporting

confidence: 68%

“…The presence of insulators improves the performance of MOSFETs due to the reduction of parasitic capacitance and enables an electrostatic control which is indispensable when downscaling the MOSFET dimensions. There are several methods for fabricating GOI substrates, such as wafer bonding (1)(2)(3)(4)(5)(6)(7)(8), Ge condensation (9)(10)(11), liquid-phase epitaxy (12,13), and separation by implanting oxygen (14,15). Among these methods, a wafer bonding technique using both Si wafers covered with SiO 2 layers and Ge wafers has an advantage that high crystalline quality of Ge layer is potentially accomplished, comparable to that of bulk Ge crystal.…”

Section: Introductionmentioning

confidence: 99%

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(Invited) GOI Substrates: Fabrication and Characterization

Sakai¹,

Yamasaka²,

Kikkawa³

et al. 2013

ECS Trans.

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Wafer bonding is an attractive process to creat new structures and materials, alternative to conventional bulk-Si substrates, in the form of substrates for the advanced metal-oxide-semiconductor field effect transistors (MOSFETs). A germanium on insulator (GOI) substrate attracts much attention because it makes the best use of the higher carrier mobility advantages compared with Si, and is suitable to further downscaling of Ge MOSFET dimensions. However, careful consideration is given especially to the bonded interface between Ge and buried oxide, which should have a device grade quality. In this work, we fabricate GOI substrates by using a wafer bonding method. Atomic structures, chemistry, and electrical properties of the Ge/BOX interface are also characterized.

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Section: Atomic and Chemical Structures Of Ge/box Interfaces In Goi Ssupporting

confidence: 68%

Section: Introductionmentioning

confidence: 99%

(Invited) GOI Substrates: Fabrication and Characterization

Sakai¹,

Yamasaka²,

Kikkawa³

et al. 2013

ECS Trans.

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“…1. Finally, the bonded wafers were annealed in N 2 atmosphere to further strengthen the bonding of the Ge/SiO 2 interface [6]. The resultant GOI substrate consisted of a sandwich structure with a top p-type Ge layer (GOI layer), buried oxide (BOX) layer, and p-type Si substrate.…”

Section: Methodsmentioning

confidence: 99%

Phonon-drag Contribution to Seebeck Coefficient of Ge-on-insulator Substrate Fabricated by Wafer Bonding Process

Veerappan¹,

Yoshida²,

Suzuki³

et al. 2015

MST

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In order to build high-sensitivity infrared photodetectors using SiGe nanowires, we investigate the thermoelectric characteristics of Ge-on-insulator (GOI) layers as a reference for SiGe. We fabricate p-type GOI substrates with an impurity concentration of 10 16 -10 18 cm -3 by a wafer-bonding process using Ge and oxidized Si wafers. Annealing treatment is performed in order to further increase the bonding strength of Ge/SiO 2 interface. We measure the Seebeck coefficient in the temperature range of 290-350 K. The Seebeck coefficient of the GOI layers is very close to the theoretical value for Ge, calculated on the basis of carrier transport. Hence, there is a small phonon-drag effect in GOI. On the other hand, the effect of phonon drag on the Seebeck coefficient of Si is usually significant. These results likely stem from the differences between phonon velocity, phonon mean-free-path, and hole mobility between Ge and Si. AbstrakKontribusi Tarikan Fonon terhadap Koefisien Seebeck Substrat Ge-On-Insulator yang Difabrikasi dengan Proses Pengikatan Wafer. Untuk membuat sebuah fotodetektor infra merah bersensitivitas tinggi dengan kawat-kawat nano SiGe, kami menyelidiki ciri-ciri termoelektrik dari lapisan-lapisan Ge-on-insulator (GOI) sebagai rujukan untuk SiGe. Kami memfabrikasi substrat-substrat GOI tipe-p dengan konsentrasi impuritas sebesar 10 16 -10 18 cm -3 melalui proses pengikatan wafer menggunakan wafer-wafer Ge dan Si yang teroksidasi. Perlakuan aniling diterapkan untuk semakin menambah kekuatan ikat antarmuka Ge/SiO 2 . Kami mengukur koefisien Seeback pada rentangan suhu 290-350 K. Koefisien Seebeck dari lapisan-lapisan GOI itu nyaris serupa dengan angka teoretis untuk Ge yang diperhitungkan berdasarkan transpor pembawa. Jadi, terdapat efek tarikan fonon kecil pada GOI. Di pihak lain, efek tarikan fonon pada koefisien Seebeck Si umumnya terjadi secara signifikan. Hasil yang demikian mungkin diakibatkan oleh perbedaan antara kecepatan fonon, jalur bebas purata fonon, dan mobilitas lubang antara Ge dan Si.

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“…This indicates a reduction in the density of interface defect states and fixed charges. Unlike the annealing effect in vacuum in our previous paper , this improvement by post‐annealing is presumably because oxygen vacancies causing oxygen deficiency near the Ge/SiO 2 interfaces introduced in the wafer‐bonding process are diminished by the oxygen supply.…”

Section: Introductionmentioning

confidence: 64%

“…Furthermore, GeOI can be applied to the pseudo-MOSFET method, which allows for easy measurement of electrical properties [17][18][19][20] without many processes necessary for the transistor fabrication. In our previous studies [21,22], we fabricated non-doped Ge(001)-OI substrates and confirmed transistor operation using the pseudo-MOSFET method. The threshold voltage shift from the ideal threshold voltage and hysteresis was observed in the channel conductance versus gate voltage curves.…”

mentioning

confidence: 89%

Improvement effect of electrical properties in post‐annealed wafer‐bonded Ge(001)‐OI substrate

Yamasaka

Nakamura²,

Yoshitake

et al. 2014

Physica Status Solidi (a)

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We investigated the electrical properties of non‐doped wafer‐bonded germanium‐on‐insulator substrates (Ge(001)‐OI) post‐annealed in various ambiences using a pseudo‐metal‐oxide‐semiconductor field effect transistor. The transistor operation in the Ge(001)‐OI without post‐annealing was observed in the n‐channel mode with hysteresis in the channel conductance versus gate voltage curves. The n‐channel transistor operation was depletion type, with a large threshold voltage shift from the ideal threshold voltage (∼0 eV). Upon post‐annealing the Ge(001)‐OI, the behavior of the hysteresis and threshold voltage shift caused by interface defects was improved, which strongly depended on the post‐annealing condition. Post‐annealing in a N2 ambience yielded the most effective improvement, which included some O2 gas. This improvement is presumably because oxygen vacancies near the Ge/SiO2 interfaces are reduced by the oxygen supply during the post‐annealing treatment.

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Annealing Effects on Ge/SiO₂ Interface Structure in Wafer-Bonded Germanium-on-Insulator Substrates

Cited by 10 publications

References 21 publications

(Invited) GOI Substrates: Fabrication and Characterization

(Invited) GOI Substrates: Fabrication and Characterization

Phonon-drag Contribution to Seebeck Coefficient of Ge-on-insulator Substrate Fabricated by Wafer Bonding Process

Improvement effect of electrical properties in post‐annealed wafer‐bonded Ge(001)‐OI substrate

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Annealing Effects on Ge/SiO2 Interface Structure in Wafer-Bonded Germanium-on-Insulator Substrates

Cited by 10 publications

References 21 publications

(Invited) GOI Substrates: Fabrication and Characterization

(Invited) GOI Substrates: Fabrication and Characterization

Phonon-drag Contribution to Seebeck Coefficient of Ge-on-insulator Substrate Fabricated by Wafer Bonding Process

Improvement effect of electrical properties in post‐annealed wafer‐bonded Ge(001)‐OI substrate

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Annealing Effects on Ge/SiO₂ Interface Structure in Wafer-Bonded Germanium-on-Insulator Substrates