Annealing effects on the conduction mechanisms of p+-amorphous- Si0.8C0.2:H/n-crystalline-Si diodes

Marsal, Lluís F.; Martı́n, I.; Pallarès, Josep; Orpella, A.; Alcubilla, R.

doi:10.1063/1.1591073

Cited by 30 publications

(31 citation statements)

References 17 publications

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“…Figure 4displays a plot of parameter A versus temperature. From this plot, the value of parameter A was nearly constant at low temperatures ranging from 200 K down to 50 K. The constant value of parameter A, together with the temperature dependent ideality factor, indicated that the mechanism of carrier transport was governed by a trap-assisted multi-step tunneling process in the hetero junctions [9][10].…”

Section: Figure III a Plot Of Ideality Factor As A Function Of Tempementioning

confidence: 82%

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Mechanism of Carrier Transport at Low Temperatures in n-Type Beta-FeSi2/p-Type Si Heterojunctions Fabricated by Facing-Target Direct-Current Sputtering

Promros¹,

Shaban²,

Baba³

et al. 2015

Advances in Intelligent Systems Research

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Abstract-The fabrication of n-type β-FeSi 2 /p-type Si hetero junctions was accomplished by FTDC Sat a substrate temperature of 600°Cwithout post-annealing. Their currentvoltage characteristic curves were measured at low temperatures ranging from 300 K down to 50 K. In order to examine the mechanism of carrier transport in the hetero junctions using thermionic emission theory, the ideality factor was estimated from the slope of the linear part of forward lnJ-V characteristic curves. In the temperature range from 300 K down to 225 K, the ideality factor was 1.23 at 300 K and increased to 2.02 at 225 K. The ideality factor values 2 implied that the mechanism of carrier transport was governed by a recombination process. In the temperature range from 200 K down to 50 K, the ideality factor was 3.34 at 200 K and increased to 15.56at 50 K. Parameter A was calculated to be constant. The temperature dependent ideality factor, together with the constant value of parameter A, implied that the predominant mechanism of carrier transport was a trap-assisted multi-step tunneling process. At highly applied forward bias voltage, the mechanism of carrier transport was changed to a space charge limited current process.

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Section: Figure III a Plot Of Ideality Factor As A Function Of Tempementioning

confidence: 82%

“…This implied that the predominant mechanism of carrier transport in the hetero junctions was changed to another mechanism, such as space charge limited current process. Based on this process, the relation between current density and applied bias voltage is written as [10]:…”

Section: Figure IV a Plot Of Parameter A Versus Temperaturementioning

confidence: 99%

Mechanism of Carrier Transport at Low Temperatures in n-Type Beta-FeSi2/p-Type Si Heterojunctions Fabricated by Facing-Target Direct-Current Sputtering

Promros¹,

Shaban²,

Baba³

et al. 2015

Advances in Intelligent Systems Research

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“…The parameter X d (nanometer) is given by the expression X d = C W W PC , where W PC (nanometer) is the PDL layer thickness estimated to be 360 nm from our secondary-ion-mass spectroscopy (SIMS) profiles. 9 C W (nondimensional) reflects how steep the boron exponential profile is. In order to reproduce the experimental boron profile.…”

Section: Boron Profile In the Diffused "P…-c-si (Pdl) Layermentioning

confidence: 99%

“…The resulting boron depth profile shows an exponential profile that reaches regions further from the a-c interface at higher temperatures. 9 The doping density in a-SiC is adjusted to match the experimental dark conductivity. The stoichiometry of this film is approximately a-Si 0.8 C 0.2 : H and the dark conductivity is around 32 ⍀ cm −1 .…”

Section: A Modelingmentioning

confidence: 99%

“…In the annealed junction, the boron profile is represented by a function decaying exponentially from the a-c interface towards the c-Si bulk in agreement with experimental findings. 9 Finally, we will assume that back-surface field (BSF) is present at the back contact in order to gain insight into the full electrical potential of these structures.…”

Section: A Modelingmentioning

confidence: 99%

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Performance of annealed hybrid silicon heterojunctions: A numerical computer study

Rubinelli

Marsal

Pallarès

2005

Journal of Applied Physics

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The performance of the standard hydrogenated amorphous silicon carbon–crystalline silicon solar cell is extensively compared with the performance of a hybrid structure subjected to a high-temperature annealing processing. Our analysis indicates that high-temperature-annealed heterojunctions show more robustness in the presence of energy offsets and defective amorphous-crystalline interfaces. Annealed hybrid cells are also less vulnerable to the negative impact of amorphous silicon carbon doped layers with poor electrical properties. Furthermore, annealed structures have the potential to generate higher efficiencies than conventional heterojunctions regardless of the wafer quality. The presence of boron at the amorphous-crystalline interface and in the wafer front region plays an important role in annealed hybrid structures that are made with low-quality wafers or where there is a highly defective amorphous-crystalline interface. In this scenario, a linear boron profile in the wafer front region is more appropriate, for which there is an optimum thickness. For low defect amorphous-crystalline interfaces and high-quality wafers, a boron exponential profile is more appropriate when boron creates additional defects in the front region of the wafer. The shape of the boron profile becomes less relevant when the boron does not add additional defects to the front region of high-quality wafers and when the amorphous-crystalline interface is low defect or defect-free.

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High‐forward‐bias transport mechanism in a‐Si:H/c‐Si heterojunction solar cells

Schulze

Korte

Conrad

et al. 2010

Physica Status Solidi (a)

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In order to elucidate the transport mechanism in a-Si:H/c-Si heterojunction solar cells under high forward bias (U > 0.5 V), we conducted temperature-dependent measurements of current-voltage (I-V) curves in the dark and under illumination. ZnO:Al/(p)a-Si:H/(n)c-Si/(n þ )a-Si:H cells are compared with inversely doped structures and the impact of thin undoped a-Si:H buffer layers on charge carrier transport is explored. The solar cell I-V curves are analyzed employing a generalized twodiode model which allows fitting I-V data for a broad range of samples. The fitting results are complemented with numerical simulations using AFORS-HET under consideration of microscopic a-Si:H parameters as determined by constant-final-stateyield photoelectron spectroscopy (CFSYS) to identify possible origins for a systematic increase of the high-forward-bias ideality factor along with the open-circuit voltage (V oc ). It is further shown that also for a-Si:H/c-Si heterojunctions, dark I-V curve fit parameters can unequivocally be linked to V oc under illumination, which may prove helpful for device assessment.

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Annealing effects on the conduction mechanisms of p+-amorphous- Si0.8C0.2:H/n-crystalline-Si diodes

Cited by 30 publications

References 17 publications

Mechanism of Carrier Transport at Low Temperatures in n-Type Beta-FeSi2/p-Type Si Heterojunctions Fabricated by Facing-Target Direct-Current Sputtering

Mechanism of Carrier Transport at Low Temperatures in n-Type Beta-FeSi2/p-Type Si Heterojunctions Fabricated by Facing-Target Direct-Current Sputtering

Performance of annealed hybrid silicon heterojunctions: A numerical computer study

High‐forward‐bias transport mechanism in a‐Si:H/c‐Si heterojunction solar cells

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