Anomalous gate oxide conduction on isolation edges: analysis and process optimization

Oxide Thinning in Shallow Trench Isolation

“…However, this introduces an error of few percent on the experimental results due to a linear dependence of the conduction on the tested area and an exponential one on the oxide thickness. Our previously work [1] shows that the observed IV characteristics on STI edge intensive structures could be explained taking into account oxide thinning and poly-Si o Si substrate asperities with no further assumptions such as FN barrier lowering induced by STI stress. This work confirms the strong impact of oxide thinning on conduction and how STI stress influences the oxidation rate.…”

“…This conduction enhancement not only affects the flash device performance (for examples the average erase time, which is a direct function of the oxide thinning [1]), but also the HV oxide in the periphery. In the HV oxide, trench corner thinning of the oxide causes increased sub-threshold leakage for the transistor and lifetime reduction when used for high voltage pump application in Flash memory devices.…”

“…Poly-Si and Si substrate asperities can also contribute to the conduction [1] and become in some cases even more important than oxide thinning itself. However, in this work we focus mainly on the real oxide thinning for the stress induced by the STI formation.…”