A 65nm NOR Flash technology, featuring a true 10λ², 0.042µm² cell, is presented for the first time for 1bit/cell and 2bit/cell products. Advanced 193nm lithography, floating gate self aligned STI, cobalt salicide and three levels of copper metallization allow the integration with a high density and high performance 1.8V CMOS. IntroductionThe continuous expansion and the evolution of wireless applications ask for increasing the density and the performances of Flash memories. In this paper we present a 65nm NOR Flash technology with a cell as small as 0.042µm² (0.021µm² per bit in multilevel memories), that is the smallest presented so far (1). Use of 193nm lithography with high NA, floating gate self aligned to STI isolation, cobalt salicide and three levels of copper interconnections allow us to keep following the 10λ² roadmap for NOR cell down to this generation, integrating for the first time at this technology node high performance logic for low voltage 1.8V operation suitable for System On Chip applications.

Aim of this work was to investigate the effect of dynamic versus DC voltage stress applied to thin oxides. A longer lifetime was observed under pulsed stress at high electric fields. When increasing the fiequency we noticed an increment of lifetime and a different location of the trapped charge regardless of the stress polarity. To detect the charge trapping evolution under pulsed stress we used a new experimental procedure. Fast transitory phenomena detected using this technique are interpreted as charging and discharging of positive traps located in the anodic region. The consequent reduction of the effective positive charge allows us to explain the lifetime enhancement and the charge trapping evolution. We also compared the behaviour under pulsed stress of oxides grown in dry or steam environment. The lifetime increase is more relevant in dry oxides showing a correlation between the interface quality and the oxide reliability in dynamic mode.

A key issue for Flash cell scaling down is the reduction of tunnel oxide thickness [l]. This is mainly limited by the information loss induced by the higher gate leakage current after cycling[2], becoming critical below 1 0 m thickness. Multiple trap assisted tunneling has been proposed to model the conduction of degraded thick oxides[3], but it is not yet clear the nature of the associated defects.Data here reported are obtained on flat area capacitors with a standard full CMOS process with STI (Shallow Trench Isolation) and dual-gate technology. Tunnel oxides of 8nm thickness have been grown with different oxidation technologies. The measurement procedure is based on three steps [4] to estimate the stable charge (QstSb;J and its position [5] and the stationary SILC measured at a fixed field and extrapolated by the tunneling front model [6,7].The post oxidation treatment impacts SlLC and trapped charge and a linear correlation between SILC and bulk negative trapped charge is found (fig. I). SILC is generally associated with neutral bulk traps[3], allowing a trap assisted tunneling through the oxide. These neutral traps are created by a two-step process of anode injected hole trapping and subsequent recombination with electrons [8,9], as shown by the behavior of V(t) curve at the tum around during constant current stress. The ohsmed correlation between negative trapped charge and SlLC can be interpreted as due to the same trap, which is positively charged at low fields during SILC measurement, while it is negatively charged at the higher field used to determine the bulk trapped charge. 186-12 , I Figure 1: SUC measured at -5.3 MVIcm YS. QsmbS. with different postoxidation lreatments (at fixed t. , = 8 nm).To verify if the same trap is involved, the kinetics of the defect annealing has been carried out at different temperatures between 5 0 T and 250°C. As reported in fig. 2, SILC is indeed observed to decrease with the annealing time. In order to have a significant SILC without reaching the F-N conduction, a standard measure at -5V has been chosen. In fig. 3 the value of SlLC normalized for the SILC right afler stress is reported versus the annealing time at different temperatures. Increasing the temperature over 150°C a much stronger annealing efficiency is found. The same effect is also observed for the fixed trapped charge ( fig. 4). Both phenomena have activation energy of l.leV, similar to the Si-Si bond energy. A strong correlation between SILC and Q.a,e is found ( fig. 5): this fully confirms that the same defect is indeed responsible for the two phenomena.

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