Stress induced leakage current and bulk oxide trapping: temperature evolution

Abstract

A key issue for Flash cell scaling down is the reduction of tunnel oxide thickness [l]. This is mainly limited by the information loss induced by the higher gate leakage current after cycling[2], becoming critical below 1 0 m thickness. Multiple trap assisted tunneling has been proposed to model the conduction of degraded thick oxides[3], but it is not yet clear the nature of the associated defects.Data here reported are obtained on flat area capacitors with a standard full CMOS process with STI (Shallow Trench Isolation) and dual-gate technology. Tunnel oxides of 8nm thickness have been grown with different oxidation technologies. The measurement procedure is based on three steps [4] to estimate the stable charge (QstSb;J and its position [5] and the stationary SILC measured at a fixed field and extrapolated by the tunneling front model [6,7].The post oxidation treatment impacts SlLC and trapped charge and a linear correlation between SILC and bulk negative trapped charge is found (fig. I). SILC is generally associated with neutral bulk traps[3], allowing a trap assisted tunneling through the oxide. These neutral traps are created by a two-step process of anode injected hole trapping and subsequent recombination with electrons [8,9], as shown by the behavior of V(t) curve at the tum around during constant current stress. The ohsmed correlation between negative trapped charge and SlLC can be interpreted as due to the same trap, which is positively charged at low fields during SILC measurement, while it is negatively charged at the higher field used to determine the bulk trapped charge. 186-12 , I Figure 1: SUC measured at -5.3 MVIcm YS. QsmbS. with different postoxidation lreatments (at fixed t. , = 8 nm).To verify if the same trap is involved, the kinetics of the defect annealing has been carried out at different temperatures between 5 0 T and 250°C. As reported in fig. 2, SILC is indeed observed to decrease with the annealing time. In order to have a significant SILC without reaching the F-N conduction, a standard measure at -5V has been chosen. In fig. 3 the value of SlLC normalized for the SILC right afler stress is reported versus the annealing time at different temperatures. Increasing the temperature over 150°C a much stronger annealing efficiency is found. The same effect is also observed for the fixed trapped charge ( fig. 4). Both phenomena have activation energy of l.leV, similar to the Si-Si bond energy. A strong correlation between SILC and Q.a,e is found ( fig. 5): this fully confirms that the same defect is indeed responsible for the two phenomena.

Charge-related phenomena and reliability of non-volatile memories

“…Regarding the SILC mechanism, a strong correlation between SILC and negative bulk trapped charge has been observed [37] with the same annealing kinetics. Therefore, the same defect should be responsible for both phenomena.…”

“…Temperature has also a great impact on SILC: for temperatures below 100°C a leakage increase is found, due to higher conduction, but, increasing further the temperature, a full recovery [37] is observed with activation energy of 1.1 eV, similar to the Si-Si bond. This is a very important factor to be taken into account for avoiding too optimistic reliability evaluations in memory testing.…”

“…The negative charge annealing has an activation energy of 1.1 eV [37], the same of SILC annealing and can be used for defining a unified model in which the baking time (t bake ) and temperature (T bake ) are no longer the only parameters affecting retention after cycling, but also cycling time (t cycle ) and temperature (T cycle ) have to be considered and the resulting bake shift can be described by [7,41]: bake shift $ cycle n  ln 1 þ t bake  e Considering this normalization, all retention experiments can be unified as shown in Fig. 10b.…”

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

“…Figure 21 shows instead the dependence on the bake conditions: note that the detrapping dynamics depend on the time t 0 elapsing between the last program and the first read operation (left-hand side), resulting in a shift of the detrapping curve along the log-time axis by a quantity exactly equal to t 0 . Also, ∆V T depends upon the bake temperature T B (right-hand side of Figure 21), demonstrating that detrapping is thermally activated: the ∆V T curves at different T B are shifted according to an Arrhenius law with activation energy E A ≈ 1.1 eV [221,222,228,229], a single detrapping curve can be obtained for an equivalent T B . This value of activation energy had been also observed in earlier retention experiments [51].…”

Novel Cycling-induced Program Disturb of Split Gate Flash Memory

“…The enhanced FN tunneling during cycling leads to trap-up, the accumulation of negative trap charges on the inter-poly oxide (IPO) of the injector site and thus retards following passage of electrons [12]. Meanwhile, the FN stress on SG gate oxide during erase will result in bulk oxide traps, which is a process of anode-injected hole trapping and subsequent recombination with electrons [13]. A turn-around behavior of SG threshold is thus found.…”