Ant Colony Optimization based Module Footprint Selection and Placement for Lowering Power in Large FPGA Designs

Herath, Kalindu; Prakash, Alok; Jiang, Guiyuan; Srikanthan, Thambipillai

doi:10.1109/reconfig.2018.8641731

Cited by 3 publications

(3 citation statements)

References 15 publications

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“…However, the ANN model is specific to the target FPGA which requires a one-time training process. In [11] we presented a methodology to use the ANN based performance estimator to obtain candidate shapes and placements for all the modules in the design and hence select the best module shape and placement for each module in order to complete the compilation process. The placement decision in that work aims to lower routing power dissipation by reducing the distance between modules with higher inter- module data-flow.…”

Section: Background and Related Workmentioning

confidence: 99%

“…Fig. 14 shows the performance of benchmark applications achieved using default Quartus compilation, our preliminary subsystem mapping technique in [11] and using our subsystem mapping methodology with proposed modifications. It is evident that our methodology marginally improves frequency while significantly reducing power dissipation.…”

Section: A Evaluation Of Subsystem Grouping and Mapping Techniquementioning

confidence: 99%

“…• minimizes the distance between modules with higher inter-module data-flow, hence reducing routing power dissipation • estimates the performance of each module for different FPGA regions and shapes, and hence selects the FPGA region that gives the highest performance The proposed technique leverages the Artificial Neural Network based module performance technique proposed in [10] in order to obtain estimated performance for different FPGA regions. Preliminary investigation of this methodology was presented in [11]. In this paper we extend the approach to further reduce power consumption and improve performance (frequency) while minimizing the runtime of the proposed algorithm.…”

Section: Introductionmentioning

confidence: 99%

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First and foremost, I would like to express my heartfelt gratitude to my supervisor and mentor, Prof. Thambipillai Srikanthan, for his valuable guidance, motivation, and support for a successful and uninterrupted Ph.D. journey. Without his dedication in my research project, this Ph.D. would never be a reality. It was a complete privilege to have not only his expertise in the research domain, but also his valuable pieces of advice given as a beautiful human spirit. My warmest gratitude also goes to Dr. Alok Prakash. His enormous support and dedication throughout this research is invaluable. Brainstorming and in-depth technical discussions along with his thorough revision of research writings helped me to produce back to back publications. His assistance to me was always one step ahead of my expectations, and this gratitude will never be enough. I would also like to thank Dr. Lam Siew Kei for strengthening the research topic in the early stages. It is also impossible to forget the support given by Dr. Guiyuan in my research. My sincere appreciation also goes to Dr. Ravi Kumar Satzoda for nourishing my interests in FPGAs towards a Ph.D. I would thankfully like to remind the administrative support of Mr. Jeremiah Chua and Ms. Poh Ling. Mr. Jeremiah's swift responses in technical difficulties I encountered were always helpful. Ms. Poh Ling has always been a strength to me in policies and formalities, especially during candidature extension process when I did not see any hope. I would also like to pay my warmest appreciation for all the beautiful people in NTU canteens who always made me smile with an extra bit of food and care. I was very fortunate to have my friend, Mr. Aung Lwin Phyo beside me during the time got tough in all aspects. His warmest support assisted me in focusing on my research without any worry. His financial support during the confirmation examination is one of the best things I have ever got from a friend. My colleagues, Deshya, and Thilina, has always given their touching support to me throughout my research. Lunch breaks, coffee times with them, and xiv of course, their home-cooked treats has helped me to leave heavy minds behind. I always knew that I could count on them. My colleagues Vijeta and Supriya were sisters to me, who always approached me with the most exceptional help. My confirmation examination could not be a success without them. Max Wang's support during the last mile in this Ph.D. has comforted me to stay on track when nothing seemed to be in my favor. Thank you, all. My family has always been the greatest strength to me. Though my father is not around with me today, he has ensured I grow up this far without any hassle. My mother has given the love of both parents since my father's passing, that I found the worth in this tough journey. My two sisters, my brother, and my brother-in-law, were always my best friends that anyone can envy. Their support in this research was always silent and often disguised as a box of rice, a dessert, a car ride, or even as hidden beautiful gifts. But...

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Ant Colony Optimization based Module Footprint Selection and Placement for Lowering Power in Large FPGA Designs

Cited by 3 publications

References 15 publications

Power-Efficient Mapping of Large Applications on Modern Heterogeneous FPGAs

Power-Efficient Mapping of Large Applications on Modern Heterogeneous FPGAs

Automatic Floorplanning and Standalone Generation of Bitstream-Level IP Cores

Mapping large-scale systems on to high density FPGAs

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