Automatic Floorplanning and Standalone Generation of Bitstream-Level IP Cores

Khan, Nadir; Castro-Godínez, Jorge; Xue, Shixiang; Henkel, Jörg; Becker, Jürgen

doi:10.1109/tvlsi.2020.3023548

Cited by 6 publications

(7 citation statements)

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“…Lengauer's book [6]. While those cells typically are much smaller than a complete core, also floorplanning for a multitude of (possibly different) cores has been considered in design space exploration [7], [8]. Yet, the design goal there is often not to place the maximum number of cores, but a fixed combination of different cores that is optimal with respect to a required throughput or power consumption.…”

Section: Related Workmentioning

confidence: 99%

“…The source code of our implementation, including the other heuristics used for the evaluation, is available at https://github.com/sglitzinger/ corepacking7 https://github.com/Toblerity/Shapely 6 VOLUME 4, 2016 This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication.…”

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Packing Multiple Types of Cores for Energy-Optimized Heterogeneous Hardware-Software Co-Design of Moldable Streaming Computations

2023

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For fixed-application scenarios in embedded soft-realtime computing, the ideal (w.r.t. energy consumption) heterogeneous multi-core CPU design within given chip dimensions can be configured by composing it from given pre-layouted, rectangular chip submodules for each of a number K > 1 of core types, where K in practice is a small constant. For example, K = 2 in traditional ARM big.LITTLE designs. Nevertheless, even better solutions might be achieved for K>2, and many feasible combinations can exist. For this purpose, we investigate finding all combinations of instances of K > 1 different types of given axis-parallel rectangles that can be packed within a given fixed-size 2D rectangle, and we propose two new packing heuristics: the corner heuristic for K ≤ 4, and the onion heuristic for larger K. Both heuristics strive to pack cores of the same type close together, to simplify implementation of on-chip bus and shared cache structures. The core combinations can be used in co-optimizing chip configuration, task mapping and scheduling for stream processing applications. We evaluate the corner heuristic for a number of different types of ARM softcores and chip dimensions, and show that it outperforms strip packing techniques from the literature and yields similar results to an advanced rectpack heuristic allowing rotation, though these do not try to pack similar cores closely. INDEX TERMSPacking rectangles, heterogeneous multi-core CPU, design space exploration, hardwaresoftware co-design VOLUME 4, 2016

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Section: Related Workmentioning

confidence: 99%

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confidence: 99%

Packing Multiple Types of Cores for Energy-Optimized Heterogeneous Hardware-Software Co-Design of Moldable Streaming Computations

2023

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“…In this paper, we propose a floorplan-aware clock tree generation methodology that identifies the clocked modules in the design and floorplans of those modules for balancing the clock tree. The modules of the floorplan are initially represented as a skewed binary tree (SKB) [27]. During the perturbation of modules, our proposed methodology considers ranking the clocked modules, which will reduce the length of the clock network.…”

Section: Related Workmentioning

confidence: 99%

“…The re-positioning of these clocked modules in the floorplan results in geometric violations and increases the pre-defined width of the voltage island. This may lead to changes in the placement of modules in the neighboring voltage island that increases the routing resource in terms of wirelength [27,28]. For the purpose of quality floorplanning and to satisfy the voltage island constraint, we propose an algorithm to determine the optimal dimensions of the clocked modules in the voltage island.…”

Section: Problem Formulationmentioning

confidence: 99%

An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts

Srinath¹,

Verma

Barnawi

et al. 2021

Electronics

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Managing the timing constraints has become an important factor in the physical design of multiple supply voltage (MSV) integrated circuits (IC). Clock distribution and module scheduling are some of the conventional methods used to satisfy the timing constraints of a chip. In this paper, we propose a simulated annealing-based MSV floorplanning methodology for the design of ICs within the timing budget. Additionally, we propose a modified SKB tree representation for floorplanning the modules in the design. Our algorithm finds the optimal dimensions and position of the clocked modules in the design to reduce the wirelength and satisfy the timing constraints. The proposed algorithm is implemented in IWLS 2005 benchmark circuits and considers power, wirelength, and timing as the optimization parameters. Simulation results were obtained from the Cadence Innovus digital system taped-out at 45 nm. Our simulation results show that the proposed algorithm satisfies timing constraints through a 30.6% reduction in wirelength.

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“…+ Check author entry for coauthors He, W., see Liang, Z., TVLSI Feb. 2021 307-320 Heidarpur, M., and Mirhassani, M., An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FGPA Implementation; TVLSI April 2021 667-676 Henkel, J., see Khan, N., TVLSI Jan. 2021 1998-2002 Hosseini, M., Manjunath, N.K., Prakash, B., Mazumder, A., Chandrareddy, V., Homayoun, H., and Mohsenin, T., Cyclic Sparsely Connected Architectures for Compact Deep Convolutional Neural Networks; TVLSI Oct. 2021 1757-1770 Hou, R., see Wang, K., TVLSI Feb. 2021 347-358 Howladar, P., Roy, P., and Rahaman, H., Droplet 1922-1929 Huisken, J., see Singh, K., TVLSI June 2021 1039-1051 Hung, S., Lu, Y., Lim, S.K., and Chakrabarty, K., Power Supply Noise-Aware At-Speed Delay Fault Testing of Monolithic 3-D ICs; TVLSI 1875-1888 Hung, Y., Chen, Y., Lo, C., So, A.G., and Chang, S., Dynamic Workload Allocation for Edge Computing; TVLSI March 2021 519-529 Huo, Z., see Wang, Q., 1903-1911 Hussein, S.M., see Akbari, M., 1601-1611 Huynh, C., see Lee, S., TVLSI April 2021 739-746 Hwang, C., see Sun, Y., TVLSI June 2021 1052-1060 Hwang, J., see Song, Y., 2008-2012 Hwang, S., see Song, J., 1567-1574 Hwang, Y., see Chen, J., TVLSI July 2021 1428-1436 I Iatrou, C., see 1998-2002 Iizuka, T., see Xu, Z., 1998-2002 Stratigopoulos, H., see Elshamy, M., 2130-2142 Studer, C., see Shahabuddin, S., TVLSI April 2021 747-759 Sun, J., see Yan, C., 2003-2007 Sun, X., see Murali, G., TVLSI Feb. 2021 386-396 Sun, Y., Lee, J., and Hwang, C., A Generalized Power Supply Induced Jitter Model Based on Power Supply Rejection Ratio Response; TVLSI June 2021 1052-1060 Sunny, F.P., Mirza, A., Thakkar, I., Nikdast, M., and Pasricha, S. 2197-2209 Tang, H., see Zhuang, H., TVLSI July 2021 1485-1489 Tang, H., see Lu, Z., 1591-1595 Tang, K., see Yang, C., TVLSI Aug. 20211575-1585 Tang, K., see Akbari, M., 1601…”

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confidence: 99%

2021 Index IEEE Transactions on Very Large Scale Integration (VLSI) Systems Vol. 29

2021

IEEE Trans. VLSI Syst.

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This index covers all technical items-papers, correspondence, reviews, etc.-that appeared in this periodical during 2021, and items from previous years that were commented upon or corrected in 2021. Departments and other items may also be covered if they have been judged to have archival value.The Author Index contains the primary entry for each item, listed under the first author's name. The primary entry includes the coauthors' names, the title of the paper or other item, and its location, specified by the publication abbreviation, year, month, and inclusive pagination. The Subject Index contains entries describing the item under all appropriate subject headings, plus the first author's name, the publication abbreviation, month, and year, and inclusive pages. Note that the item title is found only under the primary entry in the Author Index.

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Automatic Floorplanning and Standalone Generation of Bitstream-Level IP Cores

Cited by 6 publications

References 33 publications

Packing Multiple Types of Cores for Energy-Optimized Heterogeneous Hardware-Software Co-Design of Moldable Streaming Computations

Packing Multiple Types of Cores for Energy-Optimized Heterogeneous Hardware-Software Co-Design of Moldable Streaming Computations

An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts

2021 Index IEEE Transactions on Very Large Scale Integration (VLSI) Systems Vol. 29

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