Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer

Hoo, Chyi-Shiang; Kanesan, Jeevan; Ganapathy, Velappa; Ramiah, Harikrishnan

doi:10.4316/aece.2013.01002

Cited by 2 publications

(1 citation statement)

References 22 publications

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“…Most of the methods use specific structures like a B-Tree (Sivaranjani and Kawya, 2013), polish notation or Corner Intersection Sequence (CIS) (Hoo et al, 2013) to internally represent a valid placement. These structures can represent a slicing floorplan where the rectangular area of placement can be recursively divided into two parts by a horizontal or vertical line, while each of the modules is within the bounds of the final rectangles produced by an algorithm (Fig.…”

Section: Known Solutionsmentioning

confidence: 99%

Ant Colony Optimisation Applied to Non-Slicing Floorplanning

Syzdykov¹,

UZBEKOV²

2015

IOI

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Abstract. In this article experimental results are provided for a very-large-scale integration (VLSI) floorplan design problem. Given is a set of modules to be placed non-overlapping on a 2-dimensional rectangular plane. We use ant system simulation as a heuristics to produce feasible layouts in order to minimize the total unused area. The algorithm differs from many others in that fact that it produces non-slicing floorplan. Our experimental results show comparable results of previous methods using ant colony optimization (ACO) in VLSI design. For this purpose we define the "interior" structure for a geometrical computation of module positions.

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Section: Known Solutionsmentioning

confidence: 99%

Ant Colony Optimisation Applied to Non-Slicing Floorplanning

Syzdykov¹,

UZBEKOV²

2015

IOI

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Cost reduction in bottom‐up hierarchical‐based VLSI floorplanning designs

Hoo

Kanesan

Ramiah

2013

Circuit Theory & Apps

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From the industrial perspective, floorplanning is a crucial step in the VLSI physical design process as its efficiency determines the quality and the time-to-market of the product. A new perturbation method, called Cull-and-Aggregate Bottom-up Floorplanner (CABF), which consists of culling and aggregating stages, is developed to perform variable-order automated floorplanning for VLSI. CABF will generate VLSI floorplan layout by calculating the modules' dimensions' differences (hard module floorplanning problems) and the modules' areas' differences (soft module floorplanning problems). Through mathematical derivation, the hard modules floorplanning area minimization cost function (two-dimensional) during culling stage is proven that a dimensional reduction can be carried out to be the difference-based cost function (one-dimensional) which simplifies the computation. During the culling stage, CABF employs linear ordering method to select and determine the order of modules where this linear runtime complexity property allows CABF to cull the modules faster. The aggregating stage of CABF will reduce the subsequent search space of this floorplanner, and the variable order aggregation enables CABF to search for the best near-optimal solution. Based on Gigascale Systems Research Center and Microelectronics Center of North Carolina circuit benchmarks, CABF gives better optimal solutions and faster runtimes for floorplanning problems involving 9 to 600 modules. This has established that CABF is performing well in respect of reliability and scalability. Besides, CABF shows its potential to be implemented in VLSI physical design as the runtime of CABF is faster with a near-optimal outcome as compared to the other existing algorithms.

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Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer

Cited by 2 publications

References 22 publications

Ant Colony Optimisation Applied to Non-Slicing Floorplanning

Ant Colony Optimisation Applied to Non-Slicing Floorplanning

Cost reduction in bottom‐up hierarchical‐based VLSI floorplanning designs

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