Antifuse field programmable gate arrays

Greene, Jonathan; Hamdy, E.; Beal, S.

doi:10.1109/5.231343

Cited by 49 publications

(33 citation statements)

References 18 publications

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“…For example, binding of look-up table FPGAs is often reduced to a decomposition in k-input bounded functions, where k depends on the technology, and is usually 4 or 5 [Cong and Ding 1992;Cong and Ding 1996]. On the other hand, Boolean matching is important for antifusebased FPGAs [Goetting et al 1995;Green et al 1993]. An antifuse-based FPGA consists of an array of programmable logic modules, each implementing a logic function that can be personalized by shorting inputs either to a voltage rail or together by programming the anti-fuses.…”

Section: Boolean Matching For Fpgasmentioning

confidence: 99%

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A survey of Boolean matching techniques for library binding

Benini

Micheli

1997

ACM Trans. Des. Autom. Electron. Syst.

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When binding a logic network to a set of cells, a fundamental problem is recognizing whether a cell can implement a portion of the network. Boolean matching means solving this task using a formalism based on Boolean algebra. In its simplest form, Boolean matching can be posed as a tautology check. We review several approaches to Boolean matching as well as to its generalization to cases involving don't care conditions and its restriction to specific libraries such as those typical of anti-fuse based FPGAs. We then present a general formulation of Boolean matching supporting multiple-output logic cells.

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Section: Boolean Matching For Fpgasmentioning

confidence: 99%

“…The uncommitted module is modeled by a combinational module function. We concentrate here on FPGAs with single-output modules [Goetting et al 1995;Green et al 1993].…”

Section: Boolean Matching For Fpgasmentioning

confidence: 99%

A survey of Boolean matching techniques for library binding

Benini

Micheli

1997

ACM Trans. Des. Autom. Electron. Syst.

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“…It uses the oxide-nitride-oxide (ONO) antifuse switch [8] to implement programmability. The wafer fabrication is done at Lockheed-Martin SEC, using a total-dose-hardened, 0.8 m-CMOS process.…”

Section: Device and Technologymentioning

confidence: 99%

Clock buffer circuit soft errors in antifuse-based field programmable gate arrays

Wang¹,

Katz

Dhaoui³

et al. 2000

IEEE Trans. Nucl. Sci.

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Three-dimensional mixed-mode device simulation is used to investigate the clock upset in an antifuse FPGA device. Two versions of the clock circuit were simulated, the original and the redesigned with improved SEU hardness. The threshold LET of each version was simulated both at static and during transition. Compared to the test data, the simulated results consistently underestimate the LET . The difference between LET at static and during transition is relatively small. This disagrees with the previous speculation that the clock upset is due to heavy-ion strikes very close to the clock edge. Efforts were also made to optimize the simulation methodology to reduce the simulation time for practicality.

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“…The programmable logic resources can be configured to implement any logic function, while the interconnects provide the flexibility to connect any signal in the design to any logic resource. The programming technology for the logic and interconnect resources can be Static Random Access Memory (SRAM), flash memory [6], or antifuse [7,8]. SRAM-based FPGAs offer incircuit reconfigurability at the expense of being volatile, while antifuse are write-once devices.…”

Section: Introductionmentioning

confidence: 99%

Reduction of Power Consumption in FPGAs - An Overview

Grover¹,

Soni²

2012

IJIEEB

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-Field Programmable Gate Arrays FPGAs are highly desirable for implementation of digital systems due to their flexibility, programmability and low end product life cycle. In more than 20 years since the introduction of FPGA, research and development has produced dramatic improvements in FPGA speed and area efficiency, narrowing the gap between FPGAs and ASICs and making FPGAs the platform of choice for implementing digital circuits. FPGAs hold significant promise as a fast to market replacement. Unfortunately, the advantages of FPGAs are offset in many cases by their high power consumption and area. The goal is to reduce the power consumption without sacrificing much performance or incurring a large chip area so that the territories of FPGAs applications can expand more effectively. Reducing the power of FPGAs is the key to lowering packaging and cooling costs, improving device reliability, and opening the door to new markets such as mobile electronics. This paper presents the tips to lower down the static and dynamic power dissipation in FPGAs. It gives an overview of various techniques at system, device, and circuit and architecture level used for reduction of power consumption of FPGAs and their outcomes.

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Antifuse field programmable gate arrays

Cited by 49 publications

References 18 publications

A survey of Boolean matching techniques for library binding

A survey of Boolean matching techniques for library binding

Clock buffer circuit soft errors in antifuse-based field programmable gate arrays

Reduction of Power Consumption in FPGAs - An Overview

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