Antifuse reliability and link formation models

Abstract

Antifuse devices have been used for a variety of programmable circuits, and their application for highperformance, high density FPGA products is dramatically increasing. Attractiveness of antifuse stems from its relative small size, low ON resistance, and low OFF capacitance.Even though antifuses are conceptually simple structures, their behavior is not well understood. This report attempt to shed light into the link formation and reliability of antifuses.According to the models presented, link formation during programming is caused by melting and solidification of a-Si and portions of the electrodes. Furthermore, link switch-off failure is shown to occur at fixed voltage range caused by link melting. These models can be extended to the other types of antifuses as well.

Characterization and Modeling of a Highly Reliable ONO Antifuse for High-Performance FPGA and PROM

“…Over the past years, due to the ONO anti-fuse devices exhibiting great difference in impedance before and after programming, the anti-fuse processing technology has attracted significant attention of IC designers and manufacturers, and is widely used in the area of nonvolatile memories or programmable array logic devices for radiation-hardened space environment, such as PROM, PAL, FPGA (field programmable gate arrays), and so on [1][2][3][4][5][6]. The composition, structure, electrical characteristics and reliability of ONO antifuses have been widely studied.…”

“…The ONO dielectrics layer lies between a poly-silicon conductor and a heavily doped N+ diffusion region of the base silicon wafer. Prior to programming, the anti-fuse cell tends to exhibit very high resistance (typically >1MΩ), and the impedance may be reduced to below 1000Ω after programming under high voltage or current stress [1][2][3][4]. Under the programming voltage, the ONO sandwich melts and the base wafer grows an epitaxial "bump" into the poly-silicon in the shape of a dome.…”

“…Growth of the bump shatters the ONO layer, allowing diffusion of the substrate N+ into the poly-silicon to form a low-resistance path. The bump's size also makes the structure tolerant of current-induced stresses [1][2][3][4]. If anything, the high currents would increase the bump's size, strengthening the connection.…”