Antireflective coating optimization techniques for sub-0.2-μm geometries

Abstract

As 248nm DUV lithography is pushed to the O.18tm generation with logic features O.14tm and below, process control requirements become severe. Previously acceptable exposure latitude variations due to substrate reflectivity have become unacceptable. Additionally, next generation 248nm steppers with extremely narrow band laser illumination cause significant increases in substrate interference effects. These factors create stringent requirements for antireflective coating (ARC) optimization. We present results of experimental work to fine tune inorganic ARC thickness and optical properties for subtractive and inlaid feature types at the 0.1 8p.m generation. This work focuses on cost and time effective single wafer ARC optimization methods for extension to 300mm wafer sizes. The methods include reflectometry, spectroscopic ellipsometry, generation oftest wafers with large film thickness uniformity and calibrated simulation.

Inorganic Si-O-C Antireflection Coating at 193 nm for Cu Dual Damascene Process

“…Consequently it is difficult to achieve tight control over critical dimensions ͑CDs͒. 2 Implementing bottom antireflection coating ͑BARC͒ between the PR and the substrate can reduce CD variation by eliminating or minimizing the interface reflection. 3 Since reflectance at 193 nm is stronger than that at 248 nm, the antireflection layer ͑ARL͒ has to be used for gate and small size contact definitions.…”