AnyDSL: a partial evaluation framework for programming high-performance libraries

Leißa, Roland; Boesche, Klaas; Hack, Sebastian; Pérard-Gayot, Arsène; Membarth, Richard; Slusallek, Philipp; Müller, André C.; Schmidt, Bertil

doi:10.1145/3276489

Cited by 36 publications

(25 citation statements)

References 84 publications

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“…It takes advantage of the already proven work in AnyDSL [20], as a high design compiler, using the Impala language and partial evaluation. AnyHLS has developed its library in the field of image processing.…”

Section: Anyhlsmentioning

confidence: 99%

The review of heterogeneous design frameworks/Platforms for digital systems embedded in FPGAs and SoCs

Alali

Elmaaradi

Khaldoun

et al. 2021

IJEEI

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Systems-on-a-chip integrates specialized modules to provide well-defined functionality. To guarantee its efficiency, designers are careful to choose highlevel electronic components. In particular, FPGAs (field-programmable gate array) have demonstrated their ability to meet the requirements of emerging technology. However, traditional design methods cannot keep up with the speed and efficiency imposed by the embedded systems industry, so several frameworks have been developed to simplify the design process of an electronic system, from its modeling to its physical implementation. This paper illustrates some of them and presents a comparative study between them. Indeed, we have selected design methods of SoC (ESP4ML and HLS4ML, OpenESP, LiteX, RubyRTL, PyMTL, SysPy, PyRTL, DSSoC) and NoC networks on OCN chip (PyOCN) and in general on FPGA (PRGA, OpenFPGA, AnyHLS, PYNQ, and PyLog). The objective of this article is to analyze each tool at several levels and to discuss the benefit of each in the scientific community. We will analyze several aspects constituting the architecture and the structure of the platforms to make a comparative study of the hardware and software design flows of digital systems.

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Section: Anyhlsmentioning

confidence: 99%

The review of heterogeneous design frameworks/Platforms for digital systems embedded in FPGAs and SoCs

Alali

Elmaaradi

Khaldoun

et al. 2021

IJEEI

View full text Add to dashboard Cite

show abstract

“…These eorts are all based on parallel patterns. Another direction is to use partial evaluation as part of the framework [38], or to use a staging approach [48,52].…”

Section: Learning Autotuning and Optimizationmentioning

confidence: 99%

A vision of miking: interactive programmatic modeling, sound language composition, and self-learning compilation

Broman

2019

Proceedings of the 12th ACM SIGPLAN International Conference on Software Language Engineering

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This paper introduces a vision of Miking, a language framework for constructing ecient and sound language environments and compilers for domain-specic modeling languages. In particular, this language framework has three key objectives: (i) to automatically generate interactive programmatic modeling environments, (ii) to guarantee sound compositions of language fragments that enable both rapid and safe domain-specic language development, (iii) to include rst-class support for self-learning compilation, targeting heterogeneous execution platforms. The initiative is motivated in the domain of mathematical modeling languages. Specically, two dierent example domains are discussed: (i) modeling, simulation, and verication of cyber-physical systems, and (ii) domain-specic dierentiable probabilistic programming. The paper describes the main objectives of the vision, as well as concrete research challenges and research directions.CCS Concepts • Theory of computation → Program semantics.

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“…Recent years have witnessed the emergence of high-level approaches for high-performance computing such as Accelerate [22], Futhark [10], Delite [4], Lift [35] and AnyDSL [19]. They enable programmers to write hardware-agnostic code while putting the burden on the compiler to extract performance.…”

Section: Introductionmentioning

confidence: 99%

High-level hardware feature extraction for GPU performance prediction of stencils

Remmelg

Hagedorn

et al. 2020

Proceedings of the 13th Annual Workshop on General Purpose Processing Using Graphics Processing Unit

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High-level functional programming abstractions have started to show promising results for HPC (High-Performance Computing). Approaches such as Lift, Futhark or Delite have shown that it is possible to have both, high-level abstractions and performance, even for HPC workloads such as stencils. In addition, these highlevel functional abstractions can also be used to represent programs and their optimized variants, within the compiler itself. However, such high-level approaches rely heavily on the compiler to optimize programs which is notoriously hard when targeting GPUs.Compilers either use hand-crafted heuristics to direct the optimizations or iterative compilation to search the optimization space. The irst approach has fast compile times, however, it is not performance-portable across diferent devices and requires a lot of human efort to build the heuristics. Iterative compilation, on the other hand, has the ability to search the optimization space automatically and adapts to diferent devices. However, this process is often very time-consuming as thousands of variants have to be evaluated. Performance models based on statistical techniques have been proposed to speedup the optimization space exploration. However, they rely on low-level hardware features, in the form of performance counters or low-level static code features.Using the Lift framework, this paper demonstrates how lowlevel, GPU-speciic features are extractable directly from a highlevel functional representation. The Lift IR (Intermediate Representation) is in fact a very suitable choice since all optimization choices are exposed at the IR level. This paper shows how to extract low-level features such as number of unique cache lines accessed per warp, which is crucial for building accurate GPU performance models. Using this approach, we are able to speedup the exploration of the space by a factor 2000x on an AMD GPU and 450x on Nvidia on average across many stencil applications.

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AnyDSL: a partial evaluation framework for programming high-performance libraries

Cited by 36 publications

References 84 publications

The review of heterogeneous design frameworks/Platforms for digital systems embedded in FPGAs and SoCs

The review of heterogeneous design frameworks/Platforms for digital systems embedded in FPGAs and SoCs

A vision of miking: interactive programmatic modeling, sound language composition, and self-learning compilation

High-level hardware feature extraction for GPU performance prediction of stencils

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