AnySP: Anytime Anywhere Anyway Signal Processing

Abstract

In the past decade, the proliferation of mobile devices has increased at a spectacular rate. There are now more than 3.3 billion active cell phones in the world-a device that we now all depend on in our daily lives. The current generation of devices employs a combination of general-purpose processors, digital signal processors, and hardwired accelerators to provide giga-operations-per-second performance on milliWatt power budgets. Such heterogeneous organizations are inefficient to build and maintain, as well as waste silicon area and power. Looking forward to the next generation of mobile computing, computation requirements will increase by one to three orders of magnitude due to higher data rates, increased complexity algorithms, and greater computation diversity but the power requirements will be just as stringent. Scaling of existing approaches will not suffice instead the inherent computational efficiency, programmability, and adaptability of the hardware must change. To overcome these challenges, this paper proposes an example architecture, referred to as AnySP , for the next generation mobile signal processing. AnySP uses a co-design approach where the next generation wireless signal processing and high-definition video algorithms are analyzed to create a domain specific programmable architecture. At the heart of AnySP is a configurable single-instruction multipledata datapath that is capable of processing wide vectors or multiple narrow vectors simultaneously. In addition, deeper computation subgraphs can be pipelined across the singleinstruction multiple-data lanes. These three operating modes provide high throughput across varying application types. Results show that AnySP is capable of sustaining 4G wireless processing and high-definition video throughput rates, and will approach the 1000 Mops/mW efficiency barrier when scaled to 45nm.

Dual-Core Framework: Eliminating the Bottleneck Effect of Scalar Kernels on SIMD Architectures

“…In modern SIMD architectures [2], [3], to achieve high performance while meeting the need for real time execution, immediate exception handling is usually not supported (except for exceptions caused by external interrupts) because of the large performance loss and time uncertainty. Alternatively, exceptions are usually handled by storing the exception information in flag bits, and then software inserts trap barrier instructions to check the flag bits as needed.…”

“…Table 2 shows the area breakdown. With the instruction width set equal to that in AnySP [3], the whole overhead of the framework is about 0.14 mm 2 . With 4 SIMD cores in AnySP, the overall area overhead becomes 0.56 mm 2 , which is 4.26% of the total area of AnySPlike traditional SIMD architectures (the area of AnySP is 13.14 mm 2 ).…”

“…Examples include the stream processors [1] and GPUs. Processors from academic studies like MAVEN [2] and AnySP [3] also employ SIMD architectures. The SIMD architecture ( Fig.…”

Exploiting Both Pipelining and Data Parallelism with SIMD Reconfigurable Architecture

“…The former has micro-operation granularity such as VADD (vector add) and VMUL (vector multiply) instructions, whereas the latter has loop granularity as it applies the whole body of a loop to different iterations. SIMD processors are particularly popular and effective [11,12,13] for signal processing applications such as wireless communications and software-defined radio, and some of them [12,13] even support MIMD (Multiple Instruction Multiple Data) in addition to SIMD; however, they are all based on micro-operation granularity SIMD.…”

“…With interleaved iteration assignment, the four cores will first access A[0], A [1], A [2], and A [3], which are all in different banks, thus no bank conflict. However, with sequential iteration assignment, the cores will first access A[0], A [4], A [8], and A [12], which are all in the same bank, thus generating many bank conflicts. 2 If the stride of array access expression is greater than one (e.g., A[2i]), only some banks may have all the array elements ever accessed; others have (a) Example code (b) Bank conflict Fig.…”