Application and analysis of IDDQ diagnostic software

Nigh, P.; Forlenza, D.; Motika, Franco

doi:10.1109/test.1997.639633

Cited by 37 publications

(9 citation statements)

References 25 publications

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“…One fault model typically considered to generate test vectors for IDDQ testing is the single Pseudo Stuck-At Fault (PSF) model [11,12]. Similar to the well-known Stuck-at Fault (SF) model a fault fixes a line to a constant value.…”

Section: Fault Modelmentioning

confidence: 99%

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Targeting Leakage Constraints during ATPG

Fey

Komatsu

Furukawa

et al. 2008

2008 17th Asian Test Symposium

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In previous technology generations IDDQ testing used to be a powerful technique to detect physical faults that are not covered by standard fault models or functional tests. Due to shrinking feature sizes and consequently increasing leakage currents IDDQ testing becomes difficult in the deep-submicron area. One of the problems is the vector dependency of leakage current. Even in good devices the leakage current may vary significantly from one test vector to the next.In this work we present an ATPG framework that allows to generate test vectors within tight constraints on leakage currents. The target range for the leakage current is automatically determined. Experiments on the ITC99 benchmark suite yield testsets that achieve 100% fault coverage for the larger circuits, even when the range is narrowed down to 50% of the standard deviation of random vectors.

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Section: Fault Modelmentioning

confidence: 99%

“…Besides the PSF model, bridging faults are often considered for IDDQ testing [11,12]. The extension of the framework proposed here to handle bridging faults is straight forward and therefore not considered in more detail.…”

Section: Fault Modelmentioning

confidence: 99%

Targeting Leakage Constraints during ATPG

Fey

Komatsu

Furukawa

et al. 2008

2008 17th Asian Test Symposium

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“…Brief comparison of FedEx [8] and current method is given in Section 3. Nigh et al relied on a hierarchical approach [9], where defect analysis was applied for logic-level IDDQ testing. Here, we are considering a different problem, where shorts in CMOS circuits are targeted.…”

Section: Introductionmentioning

confidence: 99%

Layout to Logic Defect Analysis for Hierarchical Test Generation

Jenihhin

Raik

Ubar

et al. 2007

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems

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As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeting these defects, such as the bridging fault test pattern generators have been available for a long time. However, this paper proposes a new hierarchical approach based on critical area extraction for identifying the possible shorted pairs of nets on the basis of the chip layout information, combined with logiclevel test pattern generation for bridging faults. Experiments on real design layouts will show that only a fraction of all the possible pairs of nets have non-zero shorting probabilities. Furthermore, it will also be proven at the logic-level that nearly all such bridging faults can be tested by a simple and robust onepattern logic test. The methods proposed in this paper are supported by a design flow implementing existing commercial and academic CAD software.

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“…However the method does not include inter-gate bridging faults, so it can't be compared to our method which targets bridging faults. Another method was described in [10], using IB DDQ B test results and physical information (bridging fault extracted from layout). As their method requires an identical match between the devices signatures and their fault dictionary signature (and as they mention that this aspect needs to be improved), we believe that our probabilistic approach is more robust, particularly with multiple defects.…”

Section: Table 2 Emulation Results For the Combination Of The Reductmentioning

confidence: 99%

“…Fault diagnosis techniques [3][4][5][6][7][8][9][10][11][12][13][14] mainly differ from the type of defects/faults they target (e.g., delay, leakage, bridging faults), the fault models they are based on (e.g., stuck-at-fault, pseudostuck-at-fault, bridging fault, non classical models), and the information they use (e.g., logical output values, IB DDQ B ). In this paper, we specifically focus on bridging faults or defects (modeled as bridge resistors), as they still are dominant yield loss contributors.…”

Section: Introductionmentioning

confidence: 99%

3DSDM: A 3 data-source diagnostic method

Hariri

Thibeault

Proceedings. 16th IEEE Symposium on Computer Arithmetic

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The goal of this paper is to present a diagnosis method for bridging faults combining three different data sources: IB DDQ B measurements, logical behavior and layout parasitic capacitances. The resulting hybrid method constitutes a significant improvement over an existing one based on IB DDQ B probabilistic signatures. Combining these data contributes to reduce the number of potential fault sites to consider in the diagnosis process, and therefore accelerate this process. Simulation results show that the number of potential bridging fault sites is reduced from 0.5N(N-1) to less than N, where N is the number of nodes in the circuit under test.

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Application and analysis of IDDQ diagnostic software

Cited by 37 publications

References 25 publications

Targeting Leakage Constraints during ATPG

Targeting Leakage Constraints during ATPG

Layout to Logic Defect Analysis for Hierarchical Test Generation

3DSDM: A 3 data-source diagnostic method

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