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A current disadvantage of IDDq testing is lack of sojiwarebased diagnostic tools that enable IC vendors to create a large database of d q k t s uniquely detected with this test method. We present LE methodology for pe$orming defect localization based upon IDDq test injbrmation (on&). Using this technique, fault localization cafil be completed within minutes (e.g., <5 minutes) aster IC testing is complete This technique supports mzrlltiple fault models and has been successfully applied to a large number of samples--including ones that have been veriJied through jWure analysis. Data is presented related to key issues such as diagnostic resolution, hardware-to-fault model correlation, diagnostic current thresholds, and the diagnoseability of various defect types.

In this paper, a new emission-based methodfor measuring the amplitude of on-chip power supply noise is pr esented. This technique uses Time Resolved Emission (TRE) waveforms of Light Emission from Off-State Leakage Current (LEOSLC) from CMOS gates, which are used as local probe points for the noise. In order to demonstrate the capabilities of this technique, we discuss the results obtained for two early microprocessor chips fab ricated in 65 nm and 45 nm Silicon On Insulator (SOl) technologies.

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