Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment

Nigh, P.; Vallett, D.P.; Patel, A. M.; Wright, J.; Motika, Franco; Forlenza, D.; Kurtulik, R.; Wu, Chong

doi:10.1109/test.1999.805883

Cited by 35 publications

(9 citation statements)

References 15 publications

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“…The conclusions from a failure analysis study in SEMATECH 3 is reported in [Nigh98]. The testing procedures, IC stressing to achieve high reliability, characterization of the defects, fault diagnosis, and physical analysis are presented for a number of devices.…”

Section: Multi-temperature Testingmentioning

confidence: 99%

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Thermal Issues in Testing of Advanced Systems on Chip

Ghaleshahi¹

2015

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Many cutting-edge computer and electronic products are powered by advanced Systems-on-Chip (SoC). Advanced SoCs encompass superb performance together with large number of functions. This is achieved by efficient integration of huge number of transistors. Such very large scale integration is enabled by a core-based design paradigm as well as deepsubmicron and 3D-stacked-IC technologies. These technologies are susceptible to reliability and testing complications caused by thermal issues. Three crucial thermal issues related to temperature variations, temperature gradients, and temperature cycling are addressed in this thesis.Existing test scheduling techniques rely on temperature simulations to generate schedules that meet thermal constraints such as overheating prevention. The difference between the simulated temperatures and the actual temperatures is called temperature error. This error, for past technologies, is negligible. However, advanced SoCs experience large errors due to large process variations. Such large errors have costly consequences, such as overheating, and must be taken care of. This thesis presents an adaptive approach to generate test schedules that handle such temperature errors.Advanced SoCs manufactured as 3D-stacked-ICs experience large temperature gradients. Temperature gradients accelerate certain early-life defect mechanisms. These mechanisms can be accelerated using gradientbased, burn-in like operations so that the defects are detected before shipping. Moreover, temperature gradients exacerbate some delay-related defects. In order to detect such defects, testing must be performed when appropriate temperature-gradients are enforced. Schedule-based techniques that enforces the temperature-gradients for burn-in like operations and delay testing are proposed in this thesis. Abstract iiThe last thermal issue addressed by this thesis is related to temperature cycling. Temperature cycling test procedures are usually applied to safetycritical systems to detect cycling-related early-life failures. Such failures affect advanced SoCs, particularly through-silicon-via structures in 3D-stacked-ICs. An efficient schedule-based cycling-test technique that combines cycling acceleration with testing is proposed in this thesis. The proposed technique fits into existing 3D testing procedures and does not require temperature chambers. Therefore, the overall cycling acceleration and testing cost can be drastically reduced.All the proposed techniques have been implemented and evaluated with extensive experiments based on ITC'02 benchmarks as well as a number of 3D stacked ICs. Experiments show that the proposed techniques work effectively and reduce the test costs. We have also developed a fast temperature simulation technique based on a closed-form solution for the temperature equations. Experiments demonstrate that the proposed simulation technique reduces the test schedule generation time by more than half.iii Populärvetenskaplig sammanfattningMånga banbrytande dator-och elektronikprodukter drivs...

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Section: Multi-temperature Testingmentioning

confidence: 99%

“…The testing procedures, IC stressing to achieve high reliability, characterization of the defects, fault diagnosis, and physical analysis are presented for a number of devices. Testing at different temperatures is discussed in [Nigh98].…”

Section: Multi-temperature Testingmentioning

confidence: 99%

Thermal Issues in Testing of Advanced Systems on Chip

Ghaleshahi¹

2015

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“…Another important contribution is the use of critical area concepts to model the sensitivity of layout elements to defects of different sizes [145]. Finally, IBM has always complemented the modeling and theoretical analysis with empirical test effectiveness and failure analysis work [146].…”

Section: ) Defect-based Testingmentioning

confidence: 99%

EDA in IBM: past, present, and future

Darringer

Davidson

Hathaway

et al. 2000

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Throughout its history, from the early four-circuit gate-array chips of the late 1960s to today's billion-transistor multichip module, IBM has invested in tools to support its leading-edge technology and high-performance product development. The combination of demanding designs and close cooperation among product, technology, and tool development has given rise to many innovations in the electronic design automation (EDA) area and provided IBM with a significant competitive advantage. This paper highlights IBM's contributions over the last four decades and presents a view of the future, where the best methods of multimillion gate ASIC and gigahertz microprocessor design are converged to enable highly productive system-on-a-chip designs that include widely diverse hardware and software components.

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“…The threshold selection for IDDQ testing is somewhat arbitrary, and often is chosen to limit yield loss as opposed to based on physics of failures. A few studies have been done [5,16] to understand these IF devices and further investigate the question of whether or not reject these IF devices during testing. This issue is important to manufacturers as rejecting these devices would lead to unjustified yield loss and thereby revenue loss.…”

Section: Analysis Of Iddq-only Fail (If) Devicesmentioning

confidence: 99%