EDA in IBM: past, present, and future

Darringer, John A.; Davidson, E.; Hathaway, D.J.; Koenemann, B.; Lavin, Mark A.; Rahmat, K.; Roesner, Wolfgang; Schanzenbach, E. C.; Téllez, Gustavo; Trevillyan, Louise

doi:10.1109/43.898827

Cited by 44 publications

(19 citation statements)

References 116 publications

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“…Our solution was implemented for an upcoming POWER processor core design on the AWAN accelerator [6] platform. We evaluated the capability of our solution to detect bugs as well as its performance.…”

Section: Resultsmentioning

confidence: 99%

“…To boost the performance of simulation, a number of platforms have recently attracted interest as alternatives to software-based simulation: acceleration [6], emulation / proto-typing platforms [3] and post-silicon validation [11]. Hardware-accelerated simulation platforms are composed of large arrays of customized ASIC processors, specifically designed to simulate logic gates concurrently.…”

Section: Acceleration Backgroundmentioning

confidence: 99%

“…Acceleration platforms usually allow the collection and transfer of waveforms for debugging purposes [6], but the transfer slows down the simulation, eroding the key benefit of acceleration. In general, the more signals are observed and transferred, the lower the acceleration performance.…”

Section: Acceleration Backgroundmentioning

confidence: 99%

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Checking architectural outputs instruction-by-instruction on acceleration platforms

Chatterjee

Koyfman

Morad

et al. 2012

Proceedings of the 49th Annual Design Automation Conference

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Simulation-based verification is an integral part of a modern microprocessor's design effort. Commonly, several checking techniques are deployed alongside the simulator to detect and localize each functional bug manifestation. Among these, a widespread technique entails comparing a microprocessor design's outputs with a golden model at the architectural granularity, instruction-by-instruction. However, due to exponential growth in design complexity, the performance of software-based simulation falls far short of achieving an acceptable level of coverage, which typically requires billions of simulation cycles. Hence, verification engineers rely on simulation acceleration platforms. Unfortunately, the intrinsic characteristics of these platforms make the adoption of the checking solutions mentioned above a challenging goal: for instance, the lockstep execution of a software checker together with the design's simulation is no longer feasible.To address this challenge we propose an innovative solution for instruction-by-instruction (IBI) checking tailored to acceleration platforms. We provide novel design techniques to decouple event tracing from checking by including specialized tracing logic and by adding a post-simulation checking phase. Note that simulation performance in acceleration platforms degrades when increasing the number of signals that are traced; hence, it is imperative to generate a compact summary of the information required for checking, collecting and tracing only a few bits of information per cycle.

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Section: Resultsmentioning

confidence: 99%

Section: Acceleration Backgroundmentioning

confidence: 99%

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Checking architectural outputs instruction-by-instruction on acceleration platforms

Chatterjee

Koyfman

Morad

et al. 2012

Proceedings of the 49th Annual Design Automation Conference

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“…Tools for conducting system evaluation through simulation and emulation is an area of active work [25,26]. The RAMP project [27] at Berkeley is a FPGA-based many core emulation platform.…”

Section: Related Workmentioning

confidence: 99%

Experiments with the Fresh Breeze tree-based memory model

Dennis¹,

Gao

Xiao

2011

Comput Sci Res Dev

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The Fresh Breeze memory model and system architecture is proposed as an approach to achieving significant improvements in massively parallel computation by supporting fine-grain management of memory and processing resources and utilizing a global shared name space for all processors and computation tasks. Memory management and the scheduling of tasks are done by hardware realizations, eliminating nearly all operating system execution cycles for data access, task scheduling and security. In particular, the Fresh Breeze memory model uses trees of fixedsize chunks of memory to represent all data objects, which eliminates data consistency issues and simplifies memory management. Low-cost reference-count garbage collection is used to support modular programming in type-safe programming languages.The main contributions of this paper are: (1) a program exection model for massively parallel computing as the Fresh Breeze application programming interface (API) comprising a radical memory model and a scheme for expressing concurrency; (2) an experimental implementation of the API through simulation using the FAST simulator of the IBM Cyclops 64 many-core chip; (3) -mail: meng@capsl.udel.edu that demonstrate that (a) fine-grain hardware-implemented resource management mechanisms can support massive parallelism and high processor utilization through the latencyhiding properties of multi-tasking; and (b) hardware implementation of a work stealing scheme incorporated in our simulation can effectively distribute tasks over the processors of a many-core parallel computer.

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“…BACKGROUND AND RELATED WORK Acceleration and emulation platforms have become increasingly popular over the past decade and today are vital in the validation of complex designs [1,7,9,12]. Modern acceleration platforms can typically reach simulation performances between 10kHz to 1MHz by mapping a design's structural logic description to large arrays of customized processing elements and executing the simulation in a concurrent fashion [4,7,8,17].…”

Section: Introductionmentioning

confidence: 99%

ArChiVED: Architectural checking via event digests for high performance validation

Hsu

Chatterjee

Morad

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Abstract-Simulation-based techniques play a key role in validating the functional correctness of microprocessor designs. A common approach for validating microprocessors (called instruction-by-instruction, or IBI checking) consists of running a RTL and an architectural simulation in lock-step, while comparing processor architectural state at each instruction retirement. This solution, however, cannot be deployed on long regression tests, because of the limited performance of RTL simulators. Acceleration platforms have the performance power to overcome this issue, but are not amenable to the deployment of an IBI checking methodology. Indeed, validation on these platforms requires logging activity on-platform and then checking it against a golden model off-platform. Unfortunately, an IBI checking approach following this paradigm entails a large slowdown for the acceleration platform, because of the sizable amount of data that must be transferred off-platform for comparison against the golden model. In this work we propose a sequence-by-sequence (SBS) checking approach that is efficient and practical for acceleration platforms. Our solution validates the test execution over sequences of instructions (instead of individual ones), thus greatly reducing the amount of data transferred for off-platform checking. We found that SBS checking delivers the same bug-detection accuracy as traditional IBI checking, while reducing the amount of traced data by more than 90%.

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EDA in IBM: past, present, and future

Cited by 44 publications

References 116 publications

Checking architectural outputs instruction-by-instruction on acceleration platforms

Checking architectural outputs instruction-by-instruction on acceleration platforms

Experiments with the Fresh Breeze tree-based memory model

ArChiVED: Architectural checking via event digests for high performance validation

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