ArChiVED: Architectural checking via event digests for high performance validation

Abstract

Abstract-Simulation-based techniques play a key role in validating the functional correctness of microprocessor designs. A common approach for validating microprocessors (called instruction-by-instruction, or IBI checking) consists of running a RTL and an architectural simulation in lock-step, while comparing processor architectural state at each instruction retirement. This solution, however, cannot be deployed on long regression tests, because of the limited performance of RTL simulators. Acceleration platforms have the performance power to overcome this issue, but are not amenable to the deployment of an IBI checking methodology. Indeed, validation on these platforms requires logging activity on-platform and then checking it against a golden model off-platform. Unfortunately, an IBI checking approach following this paradigm entails a large slowdown for the acceleration platform, because of the sizable amount of data that must be transferred off-platform for comparison against the golden model. In this work we propose a sequence-by-sequence (SBS) checking approach that is efficient and practical for acceleration platforms. Our solution validates the test execution over sequences of instructions (instead of individual ones), thus greatly reducing the amount of data transferred for off-platform checking. We found that SBS checking delivers the same bug-detection accuracy as traditional IBI checking, while reducing the amount of traced data by more than 90%.

Methods for robust and energy - efficient microprocessor architectures

“…We define a comprehensive set of bug models in ATM hardware, which describe the effect of ATM bugs in any ISA (including x86-64, POWER8 and ARMv8 discussed previously); similarly, bug models for other parts of a microprocessor have been defined in [118] [123] [124].…”

“…Recent studies have proposed a comprehensive analysis and classification of bug models for different microprocessor hardware structures [118] [123] [124], but not for the address translation mechanisms. Recent approaches have employed the inherent ISA diversity and reversibility to generate self-checking silicon validation programs for microprocessor cores [212] [219] and other solutions that also target bugs inside the processor cores [117].…”