Checking architectural outputs instruction-by-instruction on acceleration platforms

Abstract

Simulation-based verification is an integral part of a modern microprocessor's design effort. Commonly, several checking techniques are deployed alongside the simulator to detect and localize each functional bug manifestation. Among these, a widespread technique entails comparing a microprocessor design's outputs with a golden model at the architectural granularity, instruction-by-instruction. However, due to exponential growth in design complexity, the performance of software-based simulation falls far short of achieving an acceptable level of coverage, which typically requires billions of simulation cycles. Hence, verification engineers rely on simulation acceleration platforms. Unfortunately, the intrinsic characteristics of these platforms make the adoption of the checking solutions mentioned above a challenging goal: for instance, the lockstep execution of a software checker together with the design's simulation is no longer feasible.To address this challenge we propose an innovative solution for instruction-by-instruction (IBI) checking tailored to acceleration platforms. We provide novel design techniques to decouple event tracing from checking by including specialized tracing logic and by adding a post-simulation checking phase. Note that simulation performance in acceleration platforms degrades when increasing the number of signals that are traced; hence, it is imperative to generate a compact summary of the information required for checking, collecting and tracing only a few bits of information per cycle.

ArChiVED: Architectural checking via event digests for high performance validation

“…Thus, it is compulsory to perform at least some on-platform compression using additional logic. Previous attempts to tackle this problem [6] record all events but compress data values associated with them (e.g., updated register values) using checksum schemes. The solution we propose here achieves much higher compression density by summarizing sets of events.…”

“…entails the ability to record and transfer event data off-platform at high bandwidth [6]. In contrast, our sequence-by-sequence (SBS) solution accrues and compresses several architectural events over a period of time before it transfers the information off-platform for comparison with a golden model.…”

“…We keep a few non-buggy traces to evaluate the sensitivity to false positives of our solution. Inspired by [6], we then classify the traces based on the first symptom that manifests in them:…”

“…A work-around to this limitation has been to keep these checkers off-platform; however, the overhead of transferring the monitored signal data off the platform severely limits the viability of this work-around. As a result, current industry methodologies have focused on limiting the number of synchronization events between host and platform by: i) accumulating interactions between the design and the testbench into longer and infrequent transactions [13,16], ii) synthesizing the simpler checkers into hardware for simulation alongside the design [3], or iii) recording the values of critical design signals during simulation on-platform and offloading the data at the end to check for consistency with a software checker [6]. Among these solutions, variants of the latter approach are dominant for microprocessor validation on acceleration and emulation platforms.…”

“…Among these solutions, variants of the latter approach are dominant for microprocessor validation on acceleration and emulation platforms. For instance, [6] proposes to decouple eventtracing from checking efforts. An abstraction of updates to the architectural state, non-speculative updates of register values (RU) and non-speculative instruction commits (IC), is recorded in a buffer on-platform, and then transferred off-platform to compare against the golden model events, while the test regression is run in lockstep between the two models.…”