Application and Evaluation of the RF Charge-Pumping Technique

Sasse, G.T.; Schmitz, Jurriaan

doi:10.1109/ted.2007.915088

Cited by 15 publications

(7 citation statements)

References 14 publications

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“…In the methodology used in this paper we connect the VNA in a one-port setup, thereby generating the desired voltage level at one of the signal pads of the device under test (DUT). In [2], [3] we explained the necessary calibration steps that allow to relate the measured power waves at the signal ports of the VNA to the voltage level at the DUT. The technique was then successfully applied to carry out charge pumping measurements at RF [3].…”

Section: Methodsmentioning

confidence: 99%

MOSFET Degradation Under RF Stress

Sasse

Kuper²,

Schmitz

2008

IEEE Trans. Electron Devices

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We report on the degradation of MOS transistors under RF stress. Hot-carrier degradation, NBTI and gate dielectric breakdown are investigated. The findings are compared to established voltage-and field driven models. The experimental results indicate that the existing models are well applicable into the GHz range to describe degradation of MOS transistors in an RF circuit. The probability of gate dielectric breakdown rapidly reduces at such high stress frequencies, offering added design margin for RF power circuits such as power amplifiers for mobile communication.

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Section: Methodsmentioning

confidence: 99%

MOSFET Degradation Under RF Stress

Sasse

Kuper²,

Schmitz

2008

IEEE Trans. Electron Devices

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“…Once the capture time is known, the spatial position of the trap could be calculated by means of elastic tunneling. This theory is frequently used for spatial trapping profiling by charge pumping, 6,7,12,13 and trap spectroscopy by charge injection and sensing ͑TSCIS͒, 14 and also to describe the operation of charge trap memories, 5,15 and the effect of PBTS. 16 Conventionally, the depth of traps is calculated by means of the following: ͑1͒ a Wentzel-Kramers Brillouin ͑WKB͒approximation for determination of the tunneling distance, 17 and ͑2͒ quantum considerations to calculate the lowest subband energy level in the inversion layer of the MOSFET channels.…”

Section: Emission and Capture Times At Room Temperaturementioning

confidence: 99%

Temperature dependence of the emission and capture times of SiON individual traps after positive bias temperature stress

Luque

Kaczer

Roussel

et al. 2011

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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The authors study the statistical properties of individual defects in n-type metal-oxidesemiconductor field-effect transistors ͑nMOSFETs͒ using time dependent defect spectroscopy. This technique is based on the analysis of quantized threshold voltage transients observed on nanoscaled p-type metal-oxide-semiconductor field-effect transistors ͑pMOSFETs͒ after negative stress and provides the characteristic emission and capture times of individual traps. To complement to previous studies, the authors apply the methodology to SiON nMOSFETs and positive bias temperature stress. The authors demonstrate that the relaxation transients are due to the collective behavior of individual traps. Furthermore, a strong temperature dependence is observed for both emission and capture times. This is incompatible with elastic tunneling theory which is used in trap characterization techniques such as charge pumping, and also in simulations of erase and program transients of nonvolatile memories. The calculated thermal activation energies for both times are in the order of 0.6 eV and are close to the values obtained for SiON pMOSFETs when negatively stressed.

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“…With the scaling of the oxide thickness in the sub 5nm regime, however, the increased direct tunneling leakage currents were jeopardizing the use of these techniques [18,19], and alternatives such as RF-CV [19,20] or RF Charge pumping [21] have been successfully proposed to cope with this problem. In both cases the measurement frequency was increased to compensate for the high gate leakage currents, but fundamentally the interpretation of the techniques were not changed.…”

Section: Characterization For Ge and Iii-v Mos Structuresmentioning

confidence: 99%

Trends and perspectives for electrical characterization and reliability assessment in advanced CMOS technologies

Groeseneken

Degraeve

Kaczer

et al. 2010

2010 Proceedings of the European Solid State Device Research Conference

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In this paper we give a brief historical review of the evolution of device reliability research over the past decades. Then we give some examples on how established characterization techniques that were developed for silicon based devices can be completely misinterpreted when applied to Ge or III-V based MOS-structures, and how a simple modification of the technique can ensure a correct interpretation. We also show how novel techniques, such as TSCIS (Trap spectroscopy by Charge Injection and Sensing). were developed recently to overcome the problem of dielectric material screening for logic and memory applications. With the scaling of the devices into the nanometer regime single traps are causing large variations in the device parameters, which leads to a time-dependent variability, which makes lifetime analysis difficult. Finally we show that when using the classical reliability assessment methodology based on accelerated testing, the available reliability margins are strongly reduced, in some cases even down to zero, especially for sub-1nm EOT (Effective Oxide Thickness) devices. As a result, we argue that the reliability community will have to look for alternative ways to ensure and guarantee the lifetime of future products.

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Application and Evaluation of the RF Charge-Pumping Technique

Cited by 15 publications

References 14 publications

MOSFET Degradation Under RF Stress

MOSFET Degradation Under RF Stress

Temperature dependence of the emission and capture times of SiON individual traps after positive bias temperature stress

Trends and perspectives for electrical characterization and reliability assessment in advanced CMOS technologies

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