A simulation study on a new rectifier concept is presented. This device basically consists of two gates with different workfunctions on top of a thin intrinsic or lowly doped silicon body. The workfunctions and layer thicknesses are chosen such that an electron plasma is formed on one side of the silicon body and a hole plasma on the other, i.e., a charge plasma p-n diode is formed in which no doping is required. Simulation results reveal a good rectifying behavior for well-chosen gate workfunctions and device dimensions. This concept could be applied for other semiconductor devices and materials as well in which doping is an issue.

After decades of process scaling driven by Moore's law, the silicon microelectronics world is now defined by length scales that are many times smaller than the dimensions of typical micro-optical components. This size mismatch poses an important challenge for those working to integrate photonics with complementary metal oxide semiconductor (CMOS) electronics technology. One promising solution is to fabricate optical systems at metal/dielectric interfaces, where electromagnetic modes called surface plasmon polaritons (SPPs) offer unique opportunities to confine and control light at length scales below 100 nm (refs 1, 2). Research groups working in the rapidly developing field of plasmonics have now demonstrated many passive components that suggest the potential of SPPs for applications in sensing and optical communication. Recently, active plasmonic devices based on III-V materials and organic materials have been reported. An electrical source of SPPs was recently demonstrated using organic semiconductors by Koller and colleagues. Here we show that a silicon-based electrical source for SPPs can be fabricated using established low-temperature microtechnology processes that are compatible with back-end CMOS technology.

We present a new lateral Schottky-based rectifier called the charge-plasma diode realized on ultrathin silicon-oninsulator. The device utilizes the workfunction difference between two metal contacts, palladium and erbium, and the silicon body. We demonstrate that the proposed device provides a low and constant reverse leakage-current density of about 1 fA/µm with ON/OFF current ratios of around 10 7 at 1-V forward bias and room temperature. In the forward mode, a current swing of 88 mV/dec is obtained, which is reduced to 68 mV/dec by back-gate biasing.Index Terms-Buried oxide (BOX), charge-plasma (CP) diode, diode, p-i-n diode, Schottky barrier, silicon-on-insulator (SOI).

No abstract

We present a MOS Capacitance-Voltage measurement methodology that, contrary to present methods, is highly robust against gate leakage current densities up to 1000 A/cm ¾. The methodology features specially designed RF test structures and RF measurement frequencies. It allows MOS parameter extraction in the full range of accumulation, depletion and inversion.