Application assessment of high throughput flip chip assembly for a high lead-eutectic solder cap interconnect system using no-flow underfill materials

Abstract

Flip chip on board (FCOB) is one of the most quickly growing segments in advanced electronic packaging. In many cases, assembly processes are not capable of providing the high throughputs needed for integrated surface mount technology (SMT) processing [1]. A new high throughput process using no-flow underfill materials has been developed that has the potential to significantly increase flip chip assembly throughput. Previous research has demonstrated the feasibility and reliability of the high throughput process required for FCOB assemblies.The goal of this research was to integrate the high throughput flip chip process on commercial flip chip packages that consisted of high lead solder balls on a polyimide passivated silicon die bonded with eutectic solder bumped pads on the laminate substrate interface [2]. This involved extensive parametric experimentation that focused on the following elements: no-flow process evaluation and implementation on the commercial packages, reflow profile parameter effects on eutectic solder wetting of high lead solder bumps, interactions between the no-flow underfill materials and the package solder interconnect and tented via features, void capture and void formation during processing, and material set compatibility and the effects on long term reliability performance.Index Terms-High lead solder bumps, underfill, void capture, void formation.

Void Formation Study of Flip Chip in Package Using No-Flow Underfill

“…Recently, a high-yield process was reported with high I/O density (over 3000 I/O) and fine pitch (down to 150 m) for full area array FCIP interconnect structures comprised of high lead solder bumps with eutectic lead-tin solder interconnects using no-flow underfill [11]- [13]. The reported reflow process conditions were optimized for the high I/O, fine-pitch FCIP assemblies using five different no-flow underfill materials for robust electrical assembly yields.…”

Near Void-Free Assembly Development of Flip Chip Using No-Flow Underfill

“…Recently, a full area-array assembly process has been reported, describing a no-flow underfill material for FCIP interconnects that use high-lead solder bumps (Pb/Sn-90/10) and eutectic lead-tin (Pb/Sn-37/63) solder paste; this was used for a flip chip device with high I/O density over 3000 I/O and fine pitch down to 150 m [3]- [5]. The systematic experiments achieved a high-speed assembly process with wide process windows, and the process was validated using a design-of-experiment (DOE) technique, but a large number of voids in the underfill material were observed, and these could cause defects such as solder bridges and solder joint cracks, possibly resulting in early failure under thermal reliability test [6]- [10].…”