With the rapid development of time-triggered network, the demand for its network performance is getting higher and higher. The transmission mechanism of time-triggered network is time-triggered mechanism, which is used to study the high-speed communication of time-triggered network. This paper proposes a high-speed communication design scheme for time-triggered network based on RGMII interface: time-triggered network transmission control module, FPGA board for time-triggered network transmission control, time-triggered encapsulation and analysis module for communication with host computer, configuration module for parameter configuration, cyclic redundancy check module for data error check. The communication between PHY layer and MAC layer is carried out by RGMII interface. Finally, simulation verification and upper board verification are carried out to realize the high-speed transmission of time-triggered network based on RGMII interface.