Application of mask process correction (MPC) to monitor and correct mask process drift

Lin, Tim; Donnelly, Tom; Russell, G.; Jung, Sunwook; Jeong, Ji-Young

doi:10.1117/12.879119

Cited by 3 publications

(2 citation statements)

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“…Recent work on mask process proximity modeling is enabling a departure from this paradigm. [35][36][37] This work involves calibrating a mask process model (MPC) based on mask CD or contour measurements, then referencing the MPC model to describe the mask input to the wafer OPC calibration flow. Figure 3 shows that a 50% reduction in mask CD variability can be realized with this approach.…”

Section: D and 2d Mask Effectsmentioning

confidence: 99%

Challenges for patterning process models applied to large scale

Sturtevant

2012

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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Full-chip patterning simulation has been utilized in semiconductor manufacturing for more than ten years, and has been a key enabler for multiple technology generations, from 130 nm to the emerging 14 nm node. This span has featured two wavelength changes, a progression of optical NA increases (and a subsequent decrease), and a variety of patterning processes and chemistries. Full-chip patterning simulations utilize quasirigorous optical models and semiempirical resist and etch process models. There has been steady improvement in the predictive power and computational efficiency of the patterning models used in full chip simulation tools, and this paper will review this progress as well as the factors that ultimately limit the predictive capability of such models. In addition, this paper will outline the new process simulation challenges that are emerging as the industry approaches sub-0.25 k1 patterning. These challenges lie principally in improving accuracy and predictive capability, including 3D effects, for an expanding set of processes and failure modes, while maintaining or improving full chip data preparation cycle times.

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Section: D and 2d Mask Effectsmentioning

confidence: 99%

Challenges for patterning process models applied to large scale

Sturtevant

2012

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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“…Ignoring the systematic mask errors incorrectly ascribes mask behavior to the photoresist model, which will necessarily limit the predictive capability of the model to some extent. Recent work on mask process proximity modeling is enabling a departure from this paradigm (9). This work involves calibrating a mask process model (MPC) based on mask CD or contour measurements, then referencing the MPC model to describe the mask input to the wafer OPC calibration flow.…”

Section: Photomaskmentioning

confidence: 99%

(Invited) Patterning Process Model Challenges for 14 Nm

Sturtevant

2013

ECS Trans.

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The taxonomy of semiconductor technology nodes has long since decoupled from the minimum critical dimension (CD) associated with the designs, but each new node nonetheless features a variety of difficult challenges. CD control and placement budgets continue to tighten with each node as new and more complex RET strategies such as multi-layer patterning, model-based assist feature, pixelated illumination sources, and negative tone develop processes are deployed. Optical Proximity Correction (OPC) is of course a vital enabler for advanced manufacturing, and OPC models describe the entire patterning process, including photomask, optics, resist, and etch as a set of separate modules. There are many factors which impact the accuracy and predictive power of these semi-empirical photomask, optical, and resist models, and care must be taken to ensure appropriate representation of all physical system parameters. These include mask critical dimension (XY) and optical (Z) properties, since 3DEMF effects are important at 14 nm node dimensions. In addition to single plane CD prediction, models must be aware of various three dimensional patterning failure modes such as SRAF printing, resist toploss, and resist pattern collapse. This paper will review the critical challenges for patterning process models for the 14 nm node.

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