Application of RHBD Techniques to SEU Hardening of Third-Generation SiGe HBT Logic Circuits

Abstract

Shift registers featuring radiation-hardening-by-design (RHBD) techniques are realized in IBM 8HP SiGe BiCMOS technology. Both circuit and device-level RHBD techniques are employed to improve the overall SEU immunity of the shift registers. Circuit-level RHBD techniques include dual-interleaving and gated-feedback that achieve SEU mitigation through local latchlevel redundancy and correction. In addition, register-level RHBD based on triple-module redundancy (TMR) versions of dual-interleaved and gated-feedback cell shift registers is also realized to gauge the performance improvement offered by TMR. At the device-level, RHBD C-BE SiGe HBTs with single collector and base contacts and significantly smaller deep trench-enclosed area than standard C-BE -B-C devices with dual collector and base contacts are used to reduce the upset sensitive area. The SEU performance of these shift registers was then tested using heavy ions and standard bit-error testing methods. The results obtained are compared to the unhardened standard shift register designed with CBEBC SiGe HBTs. The RHBD-enhanced shift registers perform significantly better than the unhardened circuit, with the TMR technique proving very effective in achieving significant SEU immunity.

RHBD Techniques to Mitigate SEU and SET in CMOS Frequency Synthesizers

“…Two RHBD circuit-redundancy techniques were employed in the FD2: Dual interlocked storage cell (DICE) [28] and gated feedback cell (GFC) [29]. In both techniques, the layout should be carefully implemented and the critical nodes should be spatially separated.…”

“…The other technique, called gated feedback cell, is also shown in Figure 8b applied to a single latch of the divider by two. The latch outputs are connected to a pair of OR gates that hold the circuit stable when an impact occurs, since the output of a two-input OR gate changes state only when both inputs change their state from high to low or from low to high [29]. The OR operation comprises a pair of source followers (M22-M25) that helps to transmit the correct logic value to the storage cell inputs even when one of the OR gate inputs is in error due to an ion strike.…”

Mitigation of Single-Event Effects in SiGe-HBT Current-Mode Logic Circuits

“…Different RHBD techniques have been proposed to mitigate SEEs in CML circuits such as device level mitigation [20][21][22], demonstrating the use of p-n-p SiGe HBTs, transistor level layout modification, and shared dummy collector for SEU mitigation. Krithivasan et al proposed the dual-interleaving and gated-feedback techniques combined, also incorporating the triple modular redundancy (TMR) technique as circuit level SEU mitigation [23] at the cost of a very high-power and area penalty. Recently, it has been demonstrated that SiGe HBTs in inverse-mode operation have improved SET response in analog and high-frequency applications [24][25][26].…”

Single-event response of the SiGe HBT in TCAD simulations and laser microbeam experiment

“…[6][7][8][9] However, recent testing and simulations have shown that SiGe HBT logic circuits could be vulnerable to the single event effect (SEE). [10][11][12][13] Considerable charge collection occurs through the reverse-biased C/S junction, resulting in the single event upset (SEU) in fast SiGe HBT digital circuits for space applications. [14] To ensure the reliability of the SiGe HBTs and circuits used in spacecraft (especially outside of spacecraft), it is necessary to carry out in-depth research about SEE on SiGe HBT.…”