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The use of δ-doping in HFET processes has made the development of transistor circuits and logic gates possible, for very high-frequency/speed or low-power applications. This behaviour of the PHFET device is due to fast quantum well conduction. However, the effect of the operating temperature range is critical. This range depends on the transistor and circuit activity, the packaging technique, and the external operating conditions. Temperature strongly affects the device ability to confine the current flow into the quantum well channel. In this paper the effect of temperature and δ-doping concentration on the performance of the device is investigated by means of simulated experiments. The results are analytically and qualitatively discussed, showing how to fine tune the δ-doping concentration in order to optimize the P-HFET behaviour from medium-to high-temperature conditions, [300, 500] K.

This paper presents a thorough study of radiation effects on a frequency synthesizer designed in a 0.18 μ m CMOS technology. In CMOS devices, the effect of a high energy particle impact can be modeled by a current pulse connected to the drain of the transistors. The effects of SET (single event transient) and SEU (single event upset) were analyzed connecting current pulses to the drains of all the transistors and analyzing the amplitude variations and phase shifts obtained at the output nodes. Following this procedure, the most sensitive circuits were detected. This paper proposes a combination of radiation hardening-by-design techniques (RHBD) such as resistor–capacitor (RC) filtering or local circuit-redundancy to mitigate the effects of radiation. The proposed modifications make the frequency synthesizer more robust against radiation.

This paper analyses the effects of single-event transients (SETs) on CMOS low noise amplifiers (LNA) designed for a 0.18 mm technology. Two well-known topologies, the common-source and common-gate cascodes, have been analysed when heavy ions strike the most sensitive nodes of these structures. In order to simulate these strikes both a physics-based technology computer aided design (TCAD) tool and an electrical circuit domain simulator have been used. This way the physics information given by the TCAD tool is combined with the fast transient simulations performed in circuit simulators. To study their SET performance, the maximum voltage peak and the recovery time of the output signal were calculated for both LNAs. Additionally, a safe operating area can be defined, setting the boundaries for acceptable SETs. Radiation hardening by design techniques have been applied at the most vulnerable nodes of both LNAs. The proposed mitigation approaches make both LNAs hardened against radiation, considerably improving their SET performance.

This paper presents a low power 2.4 GHz receiver front-end for 2.4-GHz-band IEEE 802.15.4 standard in 0.18 µm CMOS technology. This receiver adopts a low-IF architecture and comprises a variable gain single-ended low-noise amplifier (LNA), a quadrature passive mixer, a variable gain transimpedance amplifier (TIA) and a complex filter for image rejection. The receiver front-end achieves 42 dB voltage conversion gain, 10.3 dB noise figure (NF), 28 dBc image rejection and -5 dBm input third-order intercept point (IIP3). It only consumes 5.5 mW. Index terms: RF front end, CMOS RFIC, IEEE 802.15.4 receiver, low-noise amplifier (LNA), passive quadrature mixer, complex filter.