Application of workfunction engineering in vertical superjunction devices

Nautiyal, Payal; Naugarhiya, Alok; Verma, Shrish

doi:10.1016/j.spmi.2017.06.024

Cited by 15 publications

(4 citation statements)

References 19 publications

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“…Most of the authors [7,12,[16][17][18][19] have taken gate oxide thickness as 0.05μm, hence the minimum t ox of 50 nm is considered for proposed structure.…”

Section: Impact Of Vertical and Horizontal Variation Of Polysilicon L...mentioning

confidence: 99%

“…Preliminary studies suggest that research is being carried out to improve the device behavior acknowledging one or the other performance parameter [6][7][8][9][10][11][12]. Introduction of workfunction engineering at the contacts [6][7][8] was found to be one of the promising technique to reduce fabrication complexity. To enhance the current flow, the employment of SiGe layer in drift as well as channel has also been explored [9,12].…”

Section: Introductionmentioning

confidence: 99%

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Workfunction engineered stepped gate SJ UMOS with reduced specific resistance for high speed applications

Nautiyal

Naugarhiya

Verma

2019

Semicond. Sci. Technol.

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In this paper, trench superjunction MOS (SJ UMOS) utilizing workfunction engineered stepped gate for performance enhancement is proposed. N + polysilicon (Φ m =4.17 eV) layer in between two P + polysilicon (Φ m =5.25 eV) layer connected by a metal gate is incorporated in the proposed device. Additionally, gate oxide thickness is increased in steps from source to drain resulting in enhanced gate-source capacitance and reduced gate-drain capacitance. The electrical behavior of conventional and proposed device is investigated using 2D numerical simulations. The results indicate 19.5% reduction in specific resistance without degrading the breakdown voltage. Further, the proposed structure also exhibits 28.9% reduction in specific gate to drain charge, 30.5% increment in gate to source charge and 54% reduction in switching delay. In addition to this, Baliga's figure of merit (BFOM) along with other technology figure of merit (FOM) has also been evaluated, demonstrating a 26% increment in BFOM. The significant improvement in FOM is attributed to reduced specific resistance and gate to drain charge of the proposed structure. Additionally, the impact of temperature on device performance is also evaluated and no degradation in the device parameters is observed.

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“…Most of the authors [7,12,[16][17][18][19] have taken gate oxide thickness as 0.05μm, hence the minimum t ox of 50 nm is considered for proposed structure.…”

Section: Impact Of Vertical and Horizontal Variation Of Polysilicon L...mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Workfunction engineered stepped gate SJ UMOS with reduced specific resistance for high speed applications

Nautiyal

Naugarhiya

Verma

2019

Semicond. Sci. Technol.

Self Cite

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“…Nanoscale p-n diode was a primary device that is designed and fabricated applying this technique [3], [4], [5]. Doping-less bipolar transistors (BJTs), Schottky collector bipolar transistor without impurity doped emitter and base [6], [7], [8], [9], laterally singled-diffused metal oxide semiconductor, Junction-less Impact Ionization MOS, Doping-less tunnel field effect transistor and high voltage devices such as strained super-junction vertical single diffused MOSFET, silicon-based 50 V p-i-n diode [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22] are designed utilizing charge plasma concept which not only reduces the process of fabrication, but in some cases results in a better performance as compared with the conventional (doped) counterparts.…”

Section: Introductionmentioning

confidence: 99%

Doping-Less SiC p-i-n Diode: Design and Investigation

Hahmady

Bayne

2021

IEEE Access

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We introduce a novel high-voltage SiC p-i-n diode considering a charge plasma approach. This technique facilitates the formation of the anode and the cathode regions within the silicon carbide without requiring any impurity doping by taking advantage of the work-function difference between silicon carbide and metal electrodes. Utilizing the 2-D TCAD simulation, we represent the performance of the proposed doping-less silicon carbide p-i-n diode is analogous to the silicon carbide Schottky diode in terms of forward and reverse characteristics as well as temperature dependency. As opposed to the conventional (doped) silicon carbide p-i-n diode, the doping-less silicon carbide p-i-n diode holds a lower ON-state voltage drop and higher reverse saturation current. Although the doping-less silicon carbide p-i-n diode has the merits of the silicon carbide Schottky diode, but it has leverage over the corresponding counterparts by eliminating the doping and the high thermal budget fabrication processes.INDEX TERMS charge plasma, doping-less, p-i-n diode, temperature dependency,

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“…Nano scale p-n diodes have been designed and fabricated using charge plasma concept [2], [3], [4]. Lateral and vertical bipolar junction transistors (BJTs) [5], [6], [7], [8], LSMOS, SJ VSDMOS, transistirs, Bi-directional Junction-less Transistor, PIN diode, IMOS, TFETs [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20]. The CP approach not only reduces the fabrication complexity but also results in an improved performance.…”

Section: Introductionmentioning

confidence: 99%

Reverse Recovery of 50 V Silicon Charge Plasma PIN Diode

Hahmady

Bayne

2020

IEEE Access

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In this paper, a novel approach is used for the first time to design a high-voltage PIN diode without any chemical doping process of cathode and anode region. This approach favors "p" and "n" plasma region formation through various metal contacts with appropriate work-functions for anode and cathode respectively. In this study, the forward and reverse characteristics, as well as the switching performance (reverse recovery) of this novel device, charge plasma (CP) PIN diode, were compared with the Schottky diode and the conventional PIN diode using TCAD simulation.

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Application of workfunction engineering in vertical superjunction devices

Cited by 15 publications

References 19 publications

Workfunction engineered stepped gate SJ UMOS with reduced specific resistance for high speed applications

Workfunction engineered stepped gate SJ UMOS with reduced specific resistance for high speed applications

Doping-Less SiC p-i-n Diode: Design and Investigation

Reverse Recovery of 50 V Silicon Charge Plasma PIN Diode

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