Application requirements and efficiency of embedded Java bytecode multi-cores

Educating hardware design — From boolean equations to massively parallel computing systems

“…Many final projects consist of extensions or optimizations of a Java bytecode multi-core system-on-a-chip architecture [21]. In these cases the challenge lies in becoming familiar with the complex Java bytecode architecture and improving a part of it.…”

Hardware Support for Embedded Java

“…The CMP version of SHAP contains a pipelined memory arbiter and controller to optimize average case performance [73]. By using a pipelined, synchronous SRAM as main memory, the memory delivers one word per clock cycle.…”

“…Based on CLDC, the real-time specification for Java (RTSJ) [8] defines a new memory model and strengthens the scheduling guarantees to enable Java for real-time systems. Safety-critical Java (SCJ) [30] defines a subset of RTSJ for safety-critical [31,63] Xilinx FPGA 15600 LC 14 KB 30 2002 FemtoJava [6] Xilinx FPGA 2700 LC 0.5 KB 56 2003 JOP [46,50] Altera, Xilinx FPGA 3000 LC 4 KB 100 2003 jamuth [65] Altera FPGA 33 2007 BlueJEP [15] Xilinx FPGA 6900 LC 0 KB 85 2007 SHAP [72,73] Altera, Xilinx systems. Most Java processors base the Java library on CLDC or a subset of it.…”