Application Specific Datapath Extension with Distributed I/O Functional Units

Fast custom instruction identification by convex subgraph enumeration

“…However, the two problems can be directly transformed into each other (see for example, Garey and Johnson [10, p.54]). Therefore, the approach of Verma et al [15] and the approach of Pothineni et al [12] are essentially the same.…”

“…In fact, recent work [7] showed that the worst case time complexity of enumerating subgraphs having N in input and N out output operands in a DFG with N nodes is O(N Nin+Nout+1 ). Pothineni et al [12] targeted the maximal convex subgraph enumeration problem. Given a DFG, Pothineni et al first define an incompatibility graph, where the edges represent pairwise incompatibilities between DFG nodes.…”

“…Table 1 shows the solutions associated with each of these these four choices. Figure 3 shows the incompatibility graph generated by Pothineni's algorithm [12] for the DFG of Figure 2. The incompatibility graph contains seven nodes.…”

“…Although these constraints can be prohibitive on some architectures, most existing customizable processors (such as Tensilica Xtensa) allow custom instructions to have more input and out operands than the available register file ports through custom state registers that can temporarily hold some of the operands. In fact, recent work shows that input/output constraints deteriorate the solution quality on architectures where there is no explicit limit on the number of custom instruction operands [4,12,13,15]. Thus, there is a need for new algorithms that can efficiently explore custom instruction candidates within application DFGs without imposing a limit on the number of input and output operands.…”

“…Similar to the work of Pothineni [12] and the work of Verma [15], we enumerate only convex subgraphs of application DFGs that are maximal, imposing no constraints on the number of input and output operands for custom instructions. Our main contributions in this work are:…”