Application-specific instruction set processor for SoC implementation of modern signal processing algorithms

Abstract

Abstract-A novel application-specific instruction set processor (ASIP) for use in the construction of modern signal processing systems is presented. This is a flexible device that can be used in the construction of array processor systems for the real-time implementation of functions such as singular-value decomposition (SVD) and QR decomposition (QRD), as well as other important matrix computations. It uses a coordinate rotation digital computer (CORDIC) module to perform arithmetic operations and several approaches are adopted to achieve high performance including pipelining of the micro-rotations, the use of parallel instructions and a dual-bus architecture. In addition, a novel method for scale factor correction is presented which only needs to be applied once at the end of the computation. This also reduces computation time and enhances performance. Methods are described which allow this processor to be used in reduced dimension (i.e., folded) array processor structures that allow tradeoffs between hardware and performance. The net result is a flexible matrix computational processing element (PE) whose functionality can be changed under program control for use in a wider range of scenarios than previous work. Details are presented of the results of a design study, which considers the application of this decomposition PE architecture in a combined SVD/QRD system and demonstrates that a combination of high performance and efficient silicon implementation are achievable.Index Terms-Application-specific instruction set processor (ASIP), coordinate rotation digital computer (CORDIC) processors, modern signal processing, QR decomposition (QRD), singular-value decomposition (SVD), system on chip (SoC).

Multicore implementation of a multichannel parallel graphic equalizer

“…that the magnitude responses of the parallel sections meet approximately at their −3-dB points [14,27]. The transfer function (1) becomes linear in its free numerator parameters b k,0 , b k,1 , and d 0 , when the denominator coefficients are determined by the fixed poles. Writing (1) in matrix form yields where = [H( 1 ) … H( N )] T is a column vector containing the resulting frequency response of the parallel filter,…”

“…Low-power (embedded) processors play an important role for a myriad of signal processing applications, such as communications [1], image processing [2], visual detection [3], speech recognition [4], and audio processing [5], among others. In the era of smartphones and tablets, these energy-efficient architectures have increased significantly their computational capacity and are nowadays utilized in a large volume of multimedia, including video and audio processing.…”

Hardware/Software Co-reconfigurable Instruction Decoder for Adaptive Multi-core DSP Architectures

“…Application-specific instruction set processors (ASIPs) insert fixed specialized functional units, such as the Viterbi decoder, in their processors [6]. Different hardware-based reconfigurable computing techniques have been developed to meet such requirements.…”

“…Risk of code incompatibility and the burden of re-verification cost in new DSP processors create critical hindrances. Therefore, emerging DSP processors need to offer more advanced solutions for seamless support of new algorithms and applications than current approaches [6][7][8][9][10].…”

“…Based on the current trends of SoC usage, when it comes to ensuring success in today's competitive market, heterogeneous MPSoCs will be more attractive than homogeneous MPSoCs because of the inherence of their target applications, which require continuous upgrade for new standards and algorithms; they also migrate onto the contended hardware platform. These heterogeneous MPSoCs will include more application-specific/reconfigurable instruction set processors, including extensible processors [4,5] and DSPs, tightly coupled with memory hierarchies through standard and/or specific interfaces. Using reconfigurable or programmable processors in MPSoCs can offer the potential to leverage their overall performance by increasing their adaptability to target applications with flexible processing units.…”