Application Specific Processors for Multimedia Applications

Rashid, Muhammad; Apvrille, Ludovic; Pacalet, Renaud

doi:10.1109/cse.2008.26

Cited by 10 publications

(5 citation statements)

References 14 publications

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“…According to [RAP08], an ASIP is a microprocessor specialized for an application. Its instruction set is designed from scratch or extended from a known microprocessor, in order to optimize the performance of the application.…”

Section: The Goal Of Asip Designmentioning

confidence: 99%

“…The concept of ASIPs is to fill the gap between Application Specific Integrated Circuits (ASIC) and Digital Signal Processors (DSP), [RAP08]. ASICs are highly efficient, but they lack the flexibility.…”

Section: The Goal Of Asip Designmentioning

confidence: 99%

“…ASICs are highly efficient, but they lack the flexibility. On the other hand, DSPs provide software reusability with less performance and energy efficiency as compared to ASICs, [RAP08].…”

Section: The Goal Of Asip Designmentioning

confidence: 99%

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Ultra low power application specific instruction-set processor design for a cardiac beat detector algorithm

et al. 2009

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Focus: Computer architecture/arithmetic, Processor design, Continuous wavelet transform (CWT)IMEC-NL researches and develops wireless autonomous transducer solutions for Wireless Sensor Nodes (WSN) of which each component (radio, digital signal processors (DSPs), sensors, and actuators) is tailored to meet the tight power and performance constraints. The DSPs developed at IMEC-NL process the sensor node data locally, hence reducing power costly wireless data communication in order to minimize energy dissipation of the entire WSN. For this reason, the DSPs must be designed to run a specific application as efficient as possible.The assignment targets the design of an ASIP with Target processor design tools, and the research and mapping of a biomedical application on this processor. This task includes conversion of Matlab and/or generic C-code to platform related code, mapping it on a generic DSP, and retarget the DSP for the biomedical application. AbstractHigh efficiency and low power consumption are among the main topics in embedded systems today. For complex applications, off-the-shelf processor cores might not provide the desired goals in terms of power consumption.By optimizing the processor for the application, or a set of applications, one could improve the computing power by introducing special purpose hardware units. The execution cycle count of the application would in this case be reduced significantly, and the resulting processor would consume less power.In this thesis, some research is done in how to optimize a software and hardware development for ultra low power consumption. A cardiac beat detector algorithm is implemented in ANSI C, and optimized for low power consumption, by using several software power optimization techniques. The resulting application is mapped on a basic processor architecture provided by Target Compiler Technologies. This processor is optimized further for ultra low power consumption by applying application specific hardware, and by using several hardware power optimization techniques.A general processor and the optimized processor has been mapped on a chip, using a 90 nm low power TSMC process. Information about power dissipation is extracted through netlist simulation, and the results of both processors have been compared. The optimized processor consume 55% less average power, and the duty cycle of the processor, i.e., the time in which the processor executes its task with respect to the time budget available, has been reduced from 14% to 2.8%. The reduction in the total execution cycle count is 81%.The possibilities of applying power gating, or voltage and frequency scaling are discussed, and it is concluded that further reduction in power consumption is possible by applying these power optimization techniques. For a given case, the average leakage power dissipation is estimated to be reduced by 97.2%. v PrefaceDuring the work in this project, I got the opportunity to work with IMEC-NL, where I met very talented engineers and researchers. They gave me the freedom to use s...

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Section: The Goal Of Asip Designmentioning

confidence: 99%

Section: The Goal Of Asip Designmentioning

confidence: 99%

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Ultra low power application specific instruction-set processor design for a cardiac beat detector algorithm

et al. 2009

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“…Moreover, the growth in the market of mobile devices such as smart phones and tablets has led to a strong demand for lower-power and easily upgradable designs. Hence, ASIP-based implementations are becoming the key trend in system-on-a-chip (SoC) design [22]- [27].…”

Section: Introductionmentioning

confidence: 99%

“…To overcome the disadvantages of ASICs and general-purpose processors, application-specific instruction-set processor (ASIP) designs have been proposed in [22]- [24]. ASIP can have the advantages of both custom ASICs and general-purpose programmable processors.…”

Section: Introductionmentioning

confidence: 99%

MESIP: A Configurable and Data Reusable Motion Estimation Specific Instruction-Set Processor

Kim

Sunwoo

2013

IEEE Trans. Circuits Syst. Video Technol.

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This paper proposes a new motion estimation (ME)-specific instruction-set processor (MESIP) with a novel search scan order with high data reusability, to efficiently implement various advanced ME algorithms. The proposed ME-specific instructions can be selectively used for ME algorithms. The novel data-reusing search scan order, called center biased search scan (CBSS), exploits the symmetry of the search pattern to reduce redundant data loading on MESIP by about 26.9% and 16.1% compared with raster scan and snake scan, respectively. MESIP has been implemented with IBM's 90-nm CMOS technology and has 203K gates excluding memory. Simulation results show that the proposed MESIP can reduce the number of required instructions by up to 18.9% compared with existing ME processors. Moreover, MESIP achieves comparable performance even with ME ASICs and hence may be quite suitable for a low-power and high-performance ME implementation.Index Terms-Application-specific instruction-set processor (ASIP), configurable architecture, low-power design, motion estimation/motion compensation (ME/MC), search scan order.

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