Applications of DCIV method to NBTI characterization

Physical Mechanism of BTI Degradation—Direct Estimation of Trap Generation and Trapping

“…In this section, trap generation during NBTI stress in HKMG p-MOSFETs is studied using the Gated Diode or DCIV technique [7], which has been discussed in detail in Chap. 2.…”

“…2. Finally, note that DCIV scans trap generation located energetically in *0.3 eV around the Si band gap [7]. Since ΔV T gets affected by trap generation in the entire band gap, measured DCIV data must also be corrected for such band gap difference before compared to ΔV T obtained from I-V measurements.…”

“…In this section, trap generation during PBTI stress in HKMG n-MOSFETs is studied using the DCIV [7] and SILC [41] techniques. DCIV scans trap generation located energetically in *0.3 eV around the Si band gap, and in HKMG MOSFETs, it can measure generated traps at Si/IL interface, IL bulk, as well as at IL/High-K interface especially for gate stacks having thin IL layers.…”

“…While DCIV scans generated traps aligned energetically with the Si [7] mid gap, SILC scans traps closer to the conduction band edge of High-K layer, although the exact physical location of these traps are debated [41,56]. I G versus V G sweeps were taken before and during logarithmic intervals of stress, and generated trap density (ΔN OT-HK ) is calculated as discussed in Chap.…”

“…2 for accessing the density of process related and generated traps respectively before and after BTI stress. Note that direct characterization techniques such as Charge Pumping (CP) [6] and Gated Diode (or DCIV) [7] have been used in several reports to provide irrefutable proof of interface trap generation (ΔN IT ) for NBTI stress in SiON [5,[7][8][9][10][11][12][13][14][15] and HKMG [5,[16][17][18] p-MOSFETs. In spite of these experimental evidences, some reports have suggested hole trapping in pre-existing traps (ΔN HT ) as the only NBTI mechanism [19][20][21][22][23], which is definitely not correct.…”